Japan’s Advanced SoC Design Talent Incubation Program (ADIP) pairs Japanese semiconductor engineers with training from Tenstorrent. Its published advanced-track sequence is three months of pre-training in Tokyo, followed by 12 to 18 months of on-the-job training at a Tenstorrent office in the United States. Tenstorrent announced a goal of training up to 200 engineers over five years; that figure is a plan, not a verified count of participants who have completed the program.
Who runs the program, and what is it for?
Japan’s New Energy and Industrial Technology Development Organization (NEDO) commissioned ADIP. The program is led by the Leading-edge Semiconductor Technology Center (LSTC) and Tenstorrent, with the stated aim of developing practical semiconductor design engineers and architects. ADIP describes courses at entry, intermediate, and advanced levels; Tenstorrent’s U.S. on-the-job training is part of the advanced course track. ADIP’s program overview outlines its purpose and course structure.
The initiative builds on an earlier technical partnership. In February 2024, Tenstorrent announced that it and LSTC would collaborate on RISC-V and chiplet technology for Japan’s planned edge 2nm AI accelerator. That announcement establishes the broader collaboration context; it is separate from the later training-program announcement. Tenstorrent’s February 2024 announcement describes the technology partnership.
What training does the published program describe?
Tenstorrent’s current ADIP page describes a two-stage sequence: three months of pre-training in Tokyo, then 12 to 18 months of on-the-job development at a Tenstorrent U.S. office. The listed technical areas include RISC-V CPU design, AI accelerators, and chiplet implementation. Tenstorrent’s ADIP page presents these as the program’s current published training details.
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Those topics should be read as the program’s stated scope, not a promise that every participant will work on every technology. The earlier announcement named RISC-V Ascalon, Tensix IP, and AI/HPC software; the current training description uses the broader categories above. The sources do not specify individual assignments or a participant-by-participant curriculum.
How many engineers are expected to take part?
In its November 5, 2024 announcement, Tenstorrent said it could host up to 200 Japanese silicon engineers at U.S. sites over five years, and projected that the first official cohort would begin in April 2025. These are the original plan and expected start date, not evidence that 200 people enrolled or finished training. The announcement also said participants would return to their Japanese companies with knowledge of Tenstorrent’s technology and engineering practices.
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A later JETRO profile published in April 2026 described a target of developing 200 design engineers by 2029 through U.S. on-the-job training. It remains a target, not a reported completion figure. As of October 4, 2026, the cited pages do not give a verified number of people enrolled, graduated, or returned to their employers.
How does the training fit Japan’s chip strategy?
LSTC chairman Tetsuro Higashi linked the training effort to the joint work on an edge 2nm AI accelerator, saying that sending engineers to learn Tenstorrent’s technology would help grow the ecosystem and advance that effort. The training is therefore presented not only as instruction in chip design, but also as part of a broader attempt to build domestic expertise alongside a specific accelerator project. The connection reflects Higashi’s stated rationale; it does not establish a project outcome or a completed workforce target.
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What is not specified publicly?
The published material cited here does not establish full eligibility requirements, selection criteria, or individual funding terms. Nor does it confirm how many participants have started or completed the U.S. training. Those details should not be inferred from the program’s course sequence or its headline targets.
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