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On-chip ECC can detect and, for supported error patterns, correct some SRAM soft errors in commercial off-the-shelf (COTS) devices. It does not stop an upset from occurring, guarantee that every memory path is protected, or qualify a part for a radiation environment. Its value depends on the exact device, the bits and structures covered, the error patterns the code can handle, and how the system responds when correction is not possible.
What an SRAM soft error is
SRAM stores data as electrical states. An energetic particle can deposit charge near a sensitive node; if enough charge is collected, the stored state may flip. In a digital system, that is a single-event upset (SEU): a logical error that can affect data or execution without permanently damaging the chip. SRAM soft-error rate (SER) describes how often such errors occur under specified conditions. It is not a fixed property that can be applied to every device or mission.
NASA Jet Propulsion Laboratory (JPL) guidance describes estimating effects by combining information about the particle environment with measured device response. NASA’s 2025 paper on COTS system-on-chips also distinguishes transient soft errors from permanent hard errors caused by particle interactions; its results concern the particular platforms and proton conditions tested, not COTS devices as a whole.
What on-chip ECC can—and cannot—cover
Error-correcting code (ECC) stores redundant information with data. When a read or check finds a supported error pattern, the implementation may detect it, correct it, or report it. The word “on-chip” identifies where some protection logic or encoding is implemented; it does not, by itself, specify which memories, data paths, or failure modes receive protection.
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Coverage depends on the actual ECC design and integration. A code that corrects a supported single-bit error may not correct an error affecting several bits in the same codeword. Multiple-bit upsets can therefore defeat correction or produce an uncorrectable-error indication. An error in an unprotected cache, register, control state, data path, or memory interface may also fall outside SRAM ECC coverage. JPL cautions that multiple-bit upsets can make EDAC (error detection and correction) less effective when affected bits interfere with the correction code.
So ECC is a mitigation layer, not a way to prevent SER. A useful design review asks not simply whether a product advertises ECC, but what it encodes, what error patterns it detects and corrects, and what the device and system do after detection.
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A bounded product example
Microchip documents the RTAX-S FPGA family as having SEU-hardened flip-flops and error-correction encoding for embedded SRAM. This is an example of specific features in a particular family, not evidence that every memory in every configuration has identical coverage or that any RTAX-S part is qualified for a particular mission. Confirm the exact part documentation and application conditions.
Why “COTS” does not decide radiation suitability
COTS means a commercially available, generally non-custom part; it is not a radiation-tolerance rating. Nor does the label alone mean a device is unsuitable. NASA guidance treats radiation tolerance as dependent on the part and the context in which it is used. Relevant factors include the operating environment and particle population, mission duration, application criticality, and the consequences of a fault.
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A COTS-first architecture may be viable when its risks are understood and managed. NASA’s small-spacecraft avionics overview describes combining COTS equipment with radiation-hardened supporting electronics and measures such as ECC, watchdog timers, memory scrubbing, and redundancy. That approach is an architecture option, not a guarantee of mission success; the mitigation has to match the system’s failure modes and mission requirements.
How to judge SER data and test evidence
There is no generally applicable SRAM SER figure established for all COTS devices. A rate depends on factors including particle flux and energy, the device’s measured response, the amount of memory in use, operating conditions, and the time interval considered. A number without its device, environment, test method, and scope is not a sound basis for predicting a mission’s error rate.
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NASA’s Board Level Proton Testing Book of Knowledge gives report-specific estimates for worst-case SEE (single-event effect) rates in board-level analysis: about 0.1 SEE per board-day for untested boards; about 0.01 SEE per board-day after using protons near or above 200 MeV under the report’s stated approach; and below 0.001 SEE per board-day for general effects with charge-collection depth below 10 μm, with SRAM upsets among the examples. These figures are not universal SRAM rates or device-level rates. They apply to the report’s analysis and board-level context.
Board-level proton testing can inform an assessment, but its results are bounded by the tested board, setup, particle energies, and effects represented by the method. It does not automatically characterize every component or mechanism relevant to a mission. JPL’s Radiation Effects Database, described as the successor to RadCentral, states: “Absence of data for a given part or effect should not be interpreted as evidence of radiation tolerance or immunity.”
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Evidence worth requesting or checking
- Identity: exact part number, revision, configuration, and relevant device documentation.
- Test scope: whether evidence is device-level or board-level, what particle types and energies were used, and which effects were assessed.
- Memory coverage: which SRAM instances and associated paths are protected, including whether caches or other on-chip memories are covered.
- Error behavior: supported correction patterns, detection of uncorrectable errors, reporting, and any relevant recovery behavior.
- Mission match: whether the measured response and test conditions are relevant to the intended environment, operating profile, and mission duration.
Pair ECC with system-level fault handling
ECC addresses errors within its protected data path. Other mechanisms can reduce the time an error persists, identify a system that has stopped behaving correctly, or provide a way to recover. Their roles are complementary, and each has limits.
| Measure | Role | Key limit or design question |
|---|---|---|
| On-chip ECC or EDAC | Detects and may correct supported errors in encoded data. | Which memories and patterns are covered? How are uncorrectable errors handled? |
| Memory scrubbing | Periodically checks or refreshes stored data, depending on implementation, so a correctable upset can be handled before it accumulates. | What is scrubbed, how often, and what happens when an error is detected? |
| Watchdog and recovery logic | Can detect certain stalled or abnormal system states and trigger a recovery action. | Which failures are observable, and can reset or restart restore safe operation? |
| Redundancy | Can provide alternate computation, storage, or system paths for selected faults. | Are redundant elements sufficiently independent, and how are disagreements resolved? |
| Logging and fault handling | Records detected errors and supports system-level response or later diagnosis. | Can the system respond safely when an error is detected but not correctable? |
NASA mission modeling discusses cache SRAM and parity or ECC, and notes that many COTS processors do not protect their caches. This makes it important to trace the full path of state that matters to the application rather than infer coverage from the presence of ECC somewhere on the chip. Area, power, performance, and recovery overhead should be evaluated for the actual design; there is no general numeric trade-off established here.
Quick Recap
A practical design-review checklist
- Define the mission case. Record the operating environment, particle conditions that matter, expected mission duration, and application consequences of corrupted state.
- Identify the exact device. Use the specific part number and revision, not a family name or a broad “COTS” label.
- Map protected state. Determine which SRAMs and data paths use ECC, and identify relevant memories or state that do not.
- Confirm correction behavior. Establish which error patterns are detected or corrected, how multiple-bit events are handled, and what signal or action follows an uncorrectable error.
- Match evidence to use. Compare test conditions and measured response with the intended environment; distinguish device-level results from board-level estimates.
- Design the response. Decide how scrubbing, watchdogs, redundancy, logging, and recovery fit the system, including the behavior expected after detection.
- Document unknowns. Treat missing part- or effect-specific data as an evidence gap, not proof of immunity, and decide whether additional analysis or testing is warranted.
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