FPGA and PCB co-design works best when pin assignments, interfaces, electrical requirements, and board changes are managed as one shared plan—not as separate FPGA and layout tasks. Start with the target device and board requirements, exchange machine-readable pin data, check legality and electrical compatibility in both toolchains, and keep revisions synchronized. The exact constraints depend on the FPGA family and package, the interfaces, and the project.
What FPGA and PCB co-design means
FPGA I/O planning establishes how the FPGA connects to the printed circuit board and maps signals to physical package pins. AMD describes I/O and clock planning as defining and analyzing connectivity between the FPGA or ACAP and the PCB, then assigning interconnect signals to device pins in its Vivado Design Suite User Guide: I/O and Clock Planning (UG899), version 2022.2.
That makes pin planning a system-level activity shared by FPGA, PCB, and system engineers. A pin assignment may affect whether a signal can use a required dedicated resource, whether it fits an I/O bank’s capabilities, and whether the PCB can route it as intended. A file exchange feature can make the handoff easier, but it does not decide which assignment is right for a particular board.
Build the process around shared artifacts
Before choosing a toolchain, agree on which documents or files define the current design. At minimum, maintain a controlled pin map and a record of the FPGA device and package, interface signals, relevant electrical requirements, and board revision. Decide who can approve changes and how updates reach both the FPGA constraints and the schematic or layout. Vendor tools provide integration and exchange mechanisms; revision control and approval practices remain a team responsibility.
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- PCB owner: maps the agreed signals into the schematic and layout, and checks the board’s connectivity and PCB design rules.
- System owner: resolves interface, clock, power-domain, configuration, debug, and performance requirements that affect both sides.
A practical co-design workflow
1. Agree on system and interface requirements
Identify the target FPGA family, exact device and package, external interfaces, clocks, performance needs, power domains, configuration and programming approach, debug connections, and board orientation or placement assumptions. Record relevant voltage and electrical requirements alongside the interface signals. These details influence pin choices and board-level electrical behavior, so settle them before treating a pinout as final.
2. Plan pins against the actual device and board
Allocate each interface against the package pins and resources available on the selected device. Check I/O bank capabilities and voltage compatibility, dedicated-pin requirements, and the timing or placement needs of the design. Account for whether the board can place and route the proposed connections; a pinout that is legal in isolation may still be inconvenient or unsuitable for the board.
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Intel describes I/O planning as an early-stage activity. Its Quartus Prime Pro documentation covers Interface Planner for complex interfaces and Pin Planner for manual I/O placement and settings. Early planning helps uncover pin assignments that conflict with dedicated-pin, placement, or timing requirements before those assignments are embedded in the PCB design.
3. Exchange files, not just screenshots
Choose a machine-readable handoff that both toolchains and the team can review. AMD documents CSV, RTL header, and XDC exchange options for Vivado design data. These formats serve different design tasks; agree on which file is authoritative for the pin assignment, and do not assume that every format carries the same information.
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For signal-integrity work, AMD also documents exporting IBIS models for PCB analysis. An IBIS export supports that analysis; it does not replace checking the device’s electrical limits or the board’s design requirements. Intel’s Quartus Prime Pro PCB Design Tools guide documents a schematic integration flow with Cadence Allegro tools. Altium documents importing FPGA pin files and comparing FPGA signals with schematic pins. These are examples of available handoff paths, not evidence that one complete vendor pairing is best for every project.
4. Reconcile every material change in both domains
If a pin, interface, device, or relevant board assumption changes, update the agreed pin map and propagate the change to the FPGA constraints and the PCB schematic or layout. Run FPGA pin-legality checks and review the PCB mapping for signal mismatches. Keep the exported files and board revisions traceable so reviewers can tell which FPGA constraints correspond to which board design.
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Define a change-approval path for your team: who proposes a change, who checks its impact in each domain, and which revised artifacts replace the previous versions. Tool integration can compare or transfer design information, but the cited workflows do not establish your project’s revision-control process.
5. Validate electrical and board constraints
Review I/O standards, pin legality, bank-voltage compatibility, and drive or slew settings where relevant. On the PCB side, check critical routing, return paths and power needs, decoupling, configuration and debug connections, and applicable electrical and manufacturing rules. Use device-specific data sheets and board design guidelines for exact electrical limits; a pin mapper or schematic comparison is not a substitute.
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PCB rule checks and FPGA checks answer different questions. PCB design-rule workflows cover layout requirements such as routing widths and clearances; they do not, by themselves, prove FPGA pin legality or signal integrity. For critical links, use appropriate SI analysis and models, such as the IBIS export documented by AMD.
6. Repeat checks as the design evolves
Re-run the relevant checks after a material pinout, device, schematic, layout, or interface change. Keep the pin map, tool exports, FPGA constraints, and board revision aligned throughout implementation. If a prototype or board build is part of the project, treat its results as a separate validation record; tool documentation alone does not establish that a particular design has been simulated or tested successfully.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to compare toolchains
Compare toolchains against the target device and the team’s actual handoff needs. The cited documentation describes different capabilities, not a head-to-head benchmark.
| Documented path | What the documentation establishes | What to verify for your project |
|---|---|---|
| Intel Quartus Prime Pro with Cadence Allegro | The Quartus Prime Pro PCB Design Tools guide, dated 2025-05-23 and documenting version 25.1, describes an FPGA-to-PCB schematic integration flow with Cadence Allegro tools. | Support for the exact FPGA family and package, schematic workflow, exchange details, and version availability in your environment. |
| AMD Vivado data exchange and PCB analysis | Vivado Design Suite User Guide: Design Flows Overview (UG892), version 2022.2, documents CSV, RTL header, and XDC exchange options, plus IBIS export. UG899 version 2022.2 covers I/O and clock planning. | Which exchange format fits the task, how it maps into the chosen PCB EDA workflow, and whether the required model and device support are available. |
| Altium FPGA pin mapping | Altium documents importing FPGA pin information and comparing signals against schematic pins. | Current import/export steps in the installed release: the documented page includes legacy-version workflow examples. |
| Altium PCB design rules | Altium documents PCB rules such as routing widths and clearances; its article was updated 2026-09-14. | Feature availability for the product plan and version in use, and whether the rules cover the board requirements your project needs. |
Use the comparison to test a proposed workflow against the actual FPGA family and package, interface-planning needs, pin-legality checks, exchange formats, PCB EDA interoperability, constraint workflow, and SI model availability. Also verify version and licensing availability for the tools your team will use. Do not infer broader compatibility from an integration example alone.
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- Target FPGA family, device, and package are identified.
- Interfaces, clocks, power domains, configuration, and debug needs are recorded.
- Pin assignments are checked against package resources, bank capabilities, and electrical requirements.
- The authoritative pin map and the agreed exchange format are identified.
- FPGA constraints and PCB schematic or layout use the same approved pin map and revision.
- FPGA pin legality and PCB mapping mismatches have been checked.
- Relevant PCB routing, return/power, decoupling, and design-rule requirements are reviewed.
- Critical links have an appropriate SI-analysis plan and suitable models where needed.
- A named change-approval process keeps later revisions synchronized.
When a development board helps
A development board can be useful for prototyping or platform-board work, but it is not a requirement for designing a custom PCB. AMD documents a platform-board flow in UG899 version 2024.1, released 2024-05-30. Whether a development board is useful depends on the project’s prototyping and validation needs; it does not remove the need to plan and verify the target custom board’s pinout and electrical constraints.
Quick Recap
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