DRAM peripheral transistors must keep their electrical behavior after later memory-fabrication heat treatments. Meeting that requirement calls for coordinated gate-stack, junction, and contact engineering—not simply reusing a standard logic-transistor process. Planar high-k/metal-gate devices, FinFETs, and gate-first or gate-last integration each offer different performance and manufacturing trade-offs; no single flow is established here as universal.
What are DRAM peripheral transistors?
They are the transistors in the circuits that operate the memory array rather than store its bits. Those circuits include sense amplifiers, which help detect the small signals produced by memory cells, and row decoders, which select rows. Imec notes that row decoders must pass a relatively high bias for write operation. Peripheral circuitry also includes output functions.
The devices do not all have the same electrical job. Regular logic transistors may need strong short-channel control, high on-current and low off-current; other peripheral roles have their own current, voltage and threshold-voltage requirements. That variety is one reason the periphery cannot be treated as an interchangeable block of ordinary logic.
As imec puts it in “A technology platform for thermally stable DRAM peripheral transistors”: “These peripheral transistors must meet stringent requirements which preclude a ‘copy-paste’ of regular logic transistor process flows.”
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Why do DRAM peripheral transistors need to be thermally stable?
In the conventional integrated flow described by imec, peripheral transistors are fabricated before the memory elements. Subsequent processing to form the storage capacitor, access transistor and memory back end exposes those already-made devices to additional heat. Imec gives 550–600°C for several hours as a representative DRAM memory-anneal requirement; this is a fabrication process condition, not the operating temperature of a DRAM chip. The publication date of imec’s overview is not stated in the source extract.
That later heat can change the device that was deliberately formed earlier. Dopants may diffuse away from their intended source/drain profiles, affecting junction behavior. Gate materials and interfaces can shift, and source/drain contacts may become less stable or more resistive. The process challenge is to preserve the transistor’s intended electrical characteristics through the complete manufacturing sequence, not merely to make a good transistor before the memory steps occur.
A separate 2014 Microelectronic Engineering study describes long anneals in the 600–800°C range after silicide formation in its DRAM-periphery process context. That study’s range is distinct from imec’s representative 550–600°C overview figure; the two should not be combined into a single general DRAM temperature specification.
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How do process engineers protect the devices?
Imec identifies three connected areas: gate-stack engineering, junction optimization and contact integration. A choice in one module can affect the others, so the options below are process techniques rather than a universal recipe for every DRAM manufacturer.
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DRAM peripheral technology has used planar MOSFETs with poly-Si/SiO₂ or poly-Si/SiON gates and later moved toward high-k/metal-gate stacks. Later annealing can affect the gate stack, so its materials and integration sequence must be selected with the rest of the thermal budget in mind.
For high-k/metal-gate devices, a key integration choice is whether the gate is formed before high-temperature junction activation (gate-first) or replaced after much of the high-temperature processing (gate-last, also called replacement-metal-gate integration). The choice changes both the gate’s thermal exposure and the number and order of process steps.
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Junction optimization
Heat-driven dopant diffusion can blur the intended source/drain profile. Imec describes pre-amorphization implants and junction co-implants as ways to help preserve the desired dopant gradient and tune junctions for different threshold-voltage targets. These implant choices add process modules, but address a different problem from stabilizing the gate or contact.
Source/drain contact stability
Source/drain contacts need to remain stable through later anneals while keeping resistance low. Imec says conventional Ni(Pt) silicide used in logic does not tolerate the DRAM-related anneal in the process context it discusses. Its described NiPt-based module uses additional implants and annealing steps to improve stability.
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How do planar devices and FinFETs compare?
Planar high-k/metal-gate devices are a long-used approach for DRAM periphery. Imec’s overview also reports an experimentally demonstrated gate-first FinFET integration flow in 2021 and a thermally stable gate-last FinFET flow presented at IEDM in 2022. These are reported process demonstrations, not evidence that every DRAM maker uses those flows or that either is a commercial process node.
| Approach | Electrical behavior reported | Thermal and integration considerations |
|---|---|---|
| Planar high-k/metal gate | Long-used DRAM-periphery approach; comparative numeric device results are not stated in imec’s overview. | Gate stack, junctions and contacts still need to withstand later DRAM processing. Specific process-step counts are not stated (imec). |
| Gate-first FinFET | Imec reports improved on/off current and short-channel control versus planar high-k/metal-gate counterparts; numeric results are not stated in the overview. | Imec reports a 2021 experimental flow. Shared gate-stack thickness and work-function metal are used for nMOS and pMOS, with threshold-voltage shifter materials diffused into the high-k dielectric. High-temperature junction activation is associated with relatively high threshold voltage. |
| Gate-last FinFET | Imec reports a thermally stable flow presented at IEDM in 2022; comparable numeric electrical results are not stated in the overview. | Replacement-metal-gate integration can address the gate-first threshold-voltage issue, but introduces additional process steps. A specific step count is not stated (imec). |
| Separate-wafer periphery with bonding | Not stated (imec); the account presents this as an architecture direction, not a measured transistor comparison. | Fabricating periphery separately from the memory array could relax its thermal-robustness constraint; wafer bonding adds process steps. Imec describes it as a possible future direction, not established production status. |
The 2021 gate-first FinFET account describes a shared gate-stack thickness and work-function metal for nMOS and pMOS, followed by diffusion of threshold-voltage shifter materials into the high-k dielectric. Imec reports that its on/off-current and short-channel-control improvements relative to planar high-k/metal-gate counterparts did not degrade after DRAM-specific annealing, but the overview provides no underlying numeric device data.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What is the difference between gate-first and gate-last integration?
In gate-first integration, the high-k/metal gate is in place before the high-temperature junction-activation anneal. This can simplify the integration relative to a replacement-gate flow, but exposes the gate to that heat. Imec identifies relatively high threshold voltage associated with high-temperature annealing during junction activation as a drawback of its gate-first FinFET approach.
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In gate-last integration, the final metal gate is formed later through replacement-metal-gate processing. That sequence can address the gate-first threshold-voltage problem by changing when the final gate is introduced, but it adds process steps. Imec says a thermally stable gate-last FinFET flow was presented at IEDM in 2022; the available overview does not give a step count or numeric device comparison between the flows.
Thus, the choice is not simply “more advanced” versus “less advanced.” It is a balance among gate thermal exposure, threshold-voltage targets, device behavior and the complexity of integrating the flow with junction, contact and memory processing.
Could separating the periphery remove the thermal constraint?
Imec points to fabricating peripheral circuits on a separate wafer and bonding that wafer to the memory-array wafer as a possible longer-term architecture. Since the periphery would no longer be fabricated alongside the array, its transistors could face a less restrictive thermal requirement. The trade-off is the addition of wafer-bonding and associated process steps. This is described as a future direction, not as a production status claim.
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