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Power-aware verification using Common Power Format (CPF) checks how a design behaves when power domains turn off, wake up, and interact across power boundaries. It combines power intent with RTL so simulation or formal analysis can account for effects such as unknown values from an unpowered domain, isolation, and retained state. CPF-based checks are valuable for functional behavior, but they do not replace implementation-stage checks for physical power connectivity or level shifters.
What power-aware verification with CPF checks
CPF describes a design’s low-power architecture and its controls. In a power-aware verification flow, tools interpret that intent alongside the RTL, allowing engineers to check behavior in relevant power states before relying on a fully implemented netlist. For example, a powered-off block may produce unknown values; isolation and retention affect what other domains observe and what state is available after wake-up. See Prashant Bhargava’s 2008 EE Times account and Cadence’s power-aware verification methodology.
This complements ordinary functional verification: tests must exercise both intended power states and transitions between them. Power intent changes functional behavior, so verifying only the always-on state can miss problems at domain boundaries or during recovery.
Plan checks around power states and transitions
Build the plan around features, then assign checks at block and SoC level. The exact legal sequence and reset behavior depend on the design’s power architecture and supported tool constructs; define those from the project’s intent rather than assuming a universal sequence.
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- Power-down: Verify that control sequencing is legal and that the domain reaches its intended off state.
- Off-state behavior: Check what signals crossing from an off domain can present to active logic, and whether isolation takes effect at the right time.
- Power-up sequencing: Check ordering of power controls, reset, and any required initialization before consumers rely on the domain.
- Retention and restoration: Verify which state is retained, how it is restored, and what behavior is expected for state that is not retained.
- Isolation release: Check that isolation is released only when the source domain is ready to provide valid behavior.
- Return to operation: Verify reset or initialization completion and the resumption of normal transactions.
Cadence recommends planning by power feature and by block or SoC scope, then combining methods appropriate to each item. Its methodology discusses formal analysis, simulation, emulation, and prototyping on a power-aware elaboration of the design.
Choose complementary verification methods
| Method | Useful for | What it does not establish by itself |
|---|---|---|
| Formal analysis | Checking suitable properties and power-up/down sequences, including exhaustive exploration within the modeled assumptions and bounds. | It does not automatically cover every software-driven system scenario or physical implementation detail. |
| Dynamic simulation | Selected domain interactions, reset and initialization, power controls, retention behavior, and scenario-level functional tests. | Selected tests cannot guarantee that every possible sequence was exercised. |
| Emulation or FPGA prototyping | Longer hardware/software integration flows and system-level power-state behavior. | These methods do not replace the project’s structural and implementation checks. |
| Implementation and signoff checks | Physical and structural aspects of the low-power implementation, including connectivity and level-shifter concerns. | They do not replace functional verification of intended behavior across transitions. |
These distinctions describe complementary scopes, not a universal ranking of tools. Cadence’s current methodology names JasperGold for formal checks, Xcelium for CPF/UPF simulation, and emulation or FPGA prototyping for long hardware/software tests; these are vendor descriptions, not independent comparative test results. Its low-power implementation information says the solution supports CPF and IEEE 1801 power-intent formats. CPF and UPF should not be assumed identical or interchangeable in every flow: confirm the constructs and integration supported by the project’s tools.
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A practical CPF verification workflow
- Scrub the power intent. Review the CPF, or CPF/UPF flow as applicable, for consistency and confirm that the chosen tools support the constructs the design uses. Cadence recommends beginning with writing and scrubbing power intent.
- Write a feature-based plan. List power-down, off-state, sequencing, isolation, retention, reset, and recovery checks. Separate block-level responsibilities from SoC-level interactions and select a method for each.
- Prove suitable properties. Use formal analysis where applicable to check power-aware properties, unknown sources introduced by power intent, and legal power-up/down sequencing. Cadence describes these capabilities in its methodology.
- Run dynamic scenarios. Simulate relevant domain interactions, control sequences, reset and initialization, and retained-state behavior. Use emulation or prototyping when long hardware/software scenarios are needed.
- Run implementation checks separately. Check physical power connectivity and level-shifter implementation in the appropriate structural or implementation stages. Do not infer their correctness from CPF simulation alone.
- Keep regressions aligned with intent. Merge coverage across the planned checks and trigger regression when power intent changes. Cadence recommends repeating verification after such changes and automating regression triggers.
Failure cases that illustrate why transitions matter
Bhargava’s 2008 EE Times article reports several problems encountered in one live project: signals from an off block reached an always-on timer block; on-chip RAM was corrupted during power-up because the modeled sequence was incorrect; and PLL analog-model initialization signals could not recover from unknown-state propagation in that CPF simulation setup. These are historical examples from a single project, not evidence of how often such failures occur or of limitations shared by current tools.
The same article recommended retaining both CPF-based dynamic checks and Conformal Low Power static checks in a complete SoC flow. That is a historical recommendation; current flows should be planned against the project’s tools and their documented implementation and verification stages.
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Where CPF verification fits—and where it stops
CPF simulation can expose functional consequences of power sequencing and power states early, but the 2008 article explicitly says its described simulation did not check power connectivity or level shifters. Keep those concerns in the relevant implementation checks. More broadly, compare approaches by behavioral scope, abstraction level, exhaustiveness versus selected scenarios, design scale, and support for the formats and constructs actually used. No single method should be presumed to cover every axis.
For a broader reference, Springer Nature lists Progyna Khondkar’s Low-Power Design and Power-Aware Verification, whose contents include UPF modeling, power-aware standardization, dynamic simulation, coverage, and static verification.
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