Silicon engineering turns a carefully prepared silicon wafer into the patterned layers and structures used to make semiconductor devices. The wafer is the starting substrate, not a finished chip: manufacturers repeatedly add materials, print patterns, remove selected areas and adjust electrical properties to build each device layer.
What silicon engineering covers
In semiconductor manufacturing, silicon engineering includes both the wafer substrate and the fabrication operations performed on it. A wafer is a thin, highly engineered disk that supports the materials and patterns from which devices are made. SEMI describes silicon wafers as the substrate for most semiconductors and reports that industry wafers reach diameters of up to 300 mm.
The wafer itself is not a single chip. Fabrication forms many device structures across its surface; later manufacturing stages separate and package devices. The exact sequence of operations depends on the device being made, so the process below is a representative loop rather than a universal recipe.
How a representative fabrication loop works
A device is built through coordinated steps that add material, define where it should remain, remove selected material or change its electrical behavior. Microchip Technology’s manufacturing overview also includes epitaxy and planarization in its flow. Not every product uses every operation in the same order.
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1. Grow or deposit a layer
Manufacturers form films on the wafer. Deposition adds material, while epitaxy grows a crystalline layer on the substrate. Depending on the layer’s intended role, materials can provide conducting, insulating or semiconducting properties.
2. Apply photoresist and expose a pattern
A light-sensitive coating called photoresist is applied to the wafer. During lithography, a pattern is projected through a reticle onto the resist. The exposure defines where later processing will act; lithography prints the pattern but does not itself etch the underlying material.
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3. Bake and develop the resist
Baking and development prepare the exposed resist pattern, opening selected areas and protecting others. Which areas remain depends on the resist and process used.
4. Etch selected material
Etching removes exposed material in chosen regions, transferring the pattern into the layer below. It is distinct from lithography: one defines the pattern in resist, and the other removes material according to that pattern.
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5. Adjust electrical properties where needed
Ion implantation can introduce dopants into selected regions of silicon. ASML describes phosphorus and boron as examples of materials that can increase silicon’s conductive properties. Microchip’s overview groups implantation and diffusion with annealing in its process flow. The choice and placement of dopants help establish the electrical behavior required in different parts of a device.
6. Flatten or add further layers
Planarization polishes layers flat, and additional growth, deposition, lithography, etching and doping steps can follow. ASML explains that the listed manufacturing steps create a layer and are repeated to build more layers; patterning can also recur across a wafer and across device layers. The number and complexity of these operations depend on the device.
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Why the sequence repeats—and why it varies
A chip’s structures cannot usually be made with one patterning pass. Each layer may need its own material, pattern and treatment, so fabrication revisits related operations as the stack develops. Process control matters because later steps depend on the features and layers already formed. ASML says microchip manufacturing involves hundreds of steps; its explainer describes a process that can take up to four months from design to mass production. That is a broad vendor description, not a universal fab schedule. ASML’s 2025 annual report separately describes a wafer-to-finished-chip journey of up to six months, a different endpoint and framing.
Different device layers can also call for different patterning approaches. ASML distinguishes EUV lithography for the smallest features from older DUV systems used for larger ones. This is a layer- and feature-dependent process choice, not a claim that every chip uses EUV or that one lithography system is used throughout a device.
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Polished and epitaxial wafers are different categories
Wafer comparisons need to identify both the wafer type and its diameter. A polished wafer is a prepared substrate; an epitaxial wafer has an added crystalline layer grown on it. SEMI’s shipment statistics include polished, epitaxial and non-polished categories, so totals should not be read as though they describe one wafer type alone. The cited industry data cover wafer diameters up to 300 mm.
What recent wafer-market figures show
SEMI’s Silicon Manufacturers Group reported that worldwide silicon wafer shipments for semiconductor applications reached 12,973 million square inches (MSI) in 2025, up 5.8% from 2024, while revenue was $11.4 billion, down 1.2%. The results were released February 10, 2026. SEMI’s quarterly shipment series excludes solar applications, so these figures should not be generalized to all silicon wafer uses.
The different directions of shipments and revenue mean that more wafer area shipped did not translate into higher aggregate revenue in that year. The figures alone do not establish why. SEMI described demand as uneven: it reported strong demand for advanced epitaxial wafers used in logic and polished wafers for high-bandwidth memory, alongside softer demand in traditional semiconductor applications.
In a separate quarterly data point, SEMI reported 3,573 MSI of worldwide wafer shipments in Q2 2026, 7.4% higher year over year. That is a quarter-specific shipment figure, not an annual total or a revenue measure.
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