The Tool Desk
Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →Embedded World 2024 showed that embedded AI was becoming a set of practical design choices, not just a broad industry talking point. Across conference sessions and product demonstrations, vendors showed ways to run inference near the device—from tiny machine-learning models on microcontrollers to FPGA acceleration and higher-performance edge computers. The examples also made clear that an NPU is an option, not a requirement: memory, power, latency, workload and software support all help determine the right design.
Why AI was a major theme at Embedded World 2024
The Nuremberg exhibition ran from 9 to 11 April 2024. The organizer reported more than 1,100 exhibitors from almost 50 countries and well over 32,000 visitors from more than 80 countries. Its parallel conferences drew 1,871 participants and speakers from 45 countries. The organizer said the two conference keynotes, from AMD and Analog Devices, focused on “Embedded AI.” Event organizer’s 2024 report.
The pre-event conference program listed 243 presentations across 81 sessions and 18 classes. AMD’s Salil Raje was scheduled to address AI efficiency and the relationship between edge and cloud computing; Analog Devices’ Fiona Treacy was scheduled to discuss intelligent-edge approaches to sustainable factories. Official conference program.
That prominence did not mean every embedded product would use AI, or that every AI-capable product needed dedicated acceleration. Rather, the show’s examples reflected a range of choices for placing inference close to sensors, machines and users, where response time, connectivity, power and deployment requirements can matter.
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What “AI at the edge” meant on the show floor
Edge AI means running an AI model on or near the device that generates or consumes data, instead of relying entirely on a remote cloud service. In embedded systems, that can mean a small model on a microcontroller, an FPGA handling selected computations, or a larger edge platform running more demanding models. The event coverage described interest in low-power inference, software ecosystems and industrial uses, including factories that can be made more flexible through software-configurable equipment and real-time awareness. Embedded.com’s event coverage.
The approaches on display varied in compute capability and complexity. An MCU with vector processing and more memory may suit a compact workload; an NPU can accelerate supported neural-network operations; an FPGA can provide configurable logic; and a higher-performance edge computer can target larger models. These are not directly interchangeable products, and Embedded World’s demonstrations did not establish a normalized, cross-vendor performance ranking. EE Times’ product coverage.
Rank #2
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- What You Get: Anker USB-C Hub (5-in-1, 4K HDMI), welcome guide, 18-month warranty, and our friendly customer service.
Representative embedded AI approaches at Embedded World
| Approach and example | What was reported | Design consideration |
|---|---|---|
| MCU with vector processing: Ambiq Apollo510 | EE Times reported an Arm Cortex-M55 with Helium vector processing, 4 MB of on-chip NVM and 3.75 MB of SRAM. Ambiq’s NeuralSpot toolchain was also described. Ambiq claimed 10× lower latency and half the power consumption compared with Apollo4; this was a company-reported comparison, not an independent test. EE Times. | Additional memory and vector processing may be sufficient for some workloads without an NPU. Ambiq CTO Scott Hanson said that, in his view, many surveyed customer use cases could run on the M55 with extra memory. |
| FPGA acceleration: Efinix Titanium | EE Times described the Titanium family’s move to 16 nm and noted the Ti375’s PCIe, 10 Gigabit Ethernet and dual LPDDR4 interfaces. The report said Titanium 180 could accelerate tinyML workloads. A full AI software toolchain for Ti375 was still under construction at the time of the report. EE Times. | Configurable hardware can serve specialized workloads, but acceleration is only practical when the required development and deployment tools are available. |
| MCU with an NPU: Infineon PSoC Edge E8x | EE Times described an Arm Cortex-M55 paired with an Arm Ethos-U55 NPU, and reported that Infineon had acquired tinyML toolchain company Imagimob. EE Times. | An NPU provides another route to neural-network acceleration. Its usefulness depends on whether the model’s operations are supported and whether the complete software workflow fits the project. |
| Model-development and deployment workflow: NXP eIQ with NVIDIA TAO | NXP described an API-level workflow through which eIQ users could launch TAO, select or retrain models, profile them and deploy to an NXP device. The event coverage discussed model optimization and the risk that unsupported operators could fall back to CPU execution. EE Times. | Profiling and checking operator support helps establish whether the deployed model will use its intended accelerator efficiently. |
| Higher-performance edge platform: NVIDIA Jetson Orin | NVIDIA’s event page promoted partner demonstrations involving generative AI, intelligent video analytics and robotics. It described Jetson Orin as an embedded edge platform capable of running models including GPT-J and Stable Diffusion XL. NVIDIA’s Embedded World event page. | More capable platforms target larger workloads, but they are a different class of design from a low-power MCU. The event page does not establish current product availability or a like-for-like performance comparison. |
Other demonstrations illustrated the range of workloads
- Silicon Labs’ xG26 was described as having twice the Flash and RAM of its predecessor.
- Renesas demonstrated neural networks on RZ/V2H.
- An iRider e-bike advanced driver-assistance demonstration processed three camera streams using Hailo-8.
- AMD demonstrated Llama 2 7B at 2.5 tokens per second on a Ryzen Embedded 8000 processor with an NPU. This was an event demonstration reported by EE Times, not a standardized benchmark suitable for comparison with other products.
These examples span different models, devices and purposes. Without common workloads, power measurements, latency conditions and software configurations, their numbers and capabilities should not be treated as a leaderboard. EE Times’ event reporting.
Do embedded AI applications need an NPU?
No. An NPU is one possible way to accelerate supported neural-network operations, but it is not a universal requirement. A microcontroller’s CPU and vector instructions may be sufficient for a small model, particularly when the model and software are optimized and memory is adequate. For more demanding workloads, an NPU, FPGA or higher-performance edge platform may be a better fit.
Rank #3
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Ambiq CTO Scott Hanson argued that model and software optimization should come before adding an NPU. That is his view, reported by EE Times—not a settled rule for every product. The practical question is whether the complete system meets its requirements with the available compute, memory and power, and whether the chosen toolchain can deploy the model efficiently. EE Times.
How to choose an embedded AI architecture
Start with the application and the conditions in which it must run. A demo that executes a model does not, on its own, show that a design meets a product’s battery-life, thermal, response-time or reliability requirements.
Rank #4
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- Define the workload. Identify the model, input data, required accuracy and inference frequency. A tiny sensor-class model and a multi-camera vision workload make very different demands.
- Set system limits. Establish the power budget, acceptable inference latency, available memory and memory bandwidth, connectivity needs and deployment constraints. Include the impact of moving data between sensors, processors, memory and cloud services.
- Check accelerator fit. Determine whether the model’s operations are supported by the MCU’s vector instructions, NPU, FPGA or edge processor. Unsupported operations may run on the CPU instead, changing performance and energy use.
- Evaluate the software path. Confirm that tools support model conversion, optimization, profiling and deployment on the target. Quantization and pruning may help reduce model demands, but their effect on accuracy and execution must be checked for the application.
- Measure the deployed system. Profile the actual model on the intended hardware and software configuration. Compare latency, power and memory use under the conditions the product will face, rather than relying on a trade-show demonstration or vendor comparison alone.
What the event did—and did not—establish
Embedded World 2024 established that edge AI was prominent in both the formal conference program and the product demonstrations. It showed multiple architectural routes and underscored that software support and model profiling are part of the design, not afterthoughts. It did not establish that one architecture is best for all embedded AI, or provide controlled cross-vendor benchmarks. Product specifications, toolchain maturity and availability can also change; the product descriptions above refer to reporting from the April 2024 event.
Quick Recap
Best Value
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- What You Get: Anker 332 USB-C Hub (5-in-1), welcome guide, our worry-free 18-month warranty, and friendly customer service.
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