Deep ultraviolet (DUV) lithography—especially 193 nm immersion combined with multi-patterning—is the most established technology that can reduce EUV use on selected chip layers. It does so by splitting a dense pattern across multiple exposures, masks, and process steps. That makes DUV a layer-specific alternative or complement, not a demonstrated universal substitute for EUV on the smallest, most critical layers. Other approaches, including directed self-assembly and nanoimprint lithography, are better described as research-stage, complementary, or application-specific based on the available evidence.
What “less dependence on EUV” can mean
There are two distinct goals. A chipmaker can use a different exposure technology on a particular layer, reducing EUV use there. Or it can use fewer patterning steps while continuing to use EUV. The first is a possible reduction in EUV dependence; the second is a way to make EUV patterning more efficient.
The options differ in how established they are and in what role they can play:
| Technology | Potential role | What the evidence establishes |
|---|---|---|
| 193 nm DUV immersion with multi-patterning | Alternative or complement on selected layers | Established technique; requires additional exposures, masks, and process steps compared with single-patterning EUV. |
| High-NA EUV | Fewer patterning steps for some features while retaining EUV | Company roadmap describes prospective scaling and manufacturing benefits; it is not an alternative exposure technology. |
| Directed self-assembly (DSA) | Potential complementary patterning route | Research and process development are documented; broad high-volume replacement of EUV is not established. |
| Nanoimprint lithography (NIL) | Potential option for selected applications | An older roadmap discusses consideration for memory; broad leading-edge logic substitution is not established. |
| Computational lithography | Modeling and optimization for patterning processes | Supports EUV and other exposure methods; it does not expose a wafer or replace a scanner. |
DUV multi-patterning: the practical alternative on some layers
DUV uses 193 nm light, while EUV uses a much shorter wavelength. When one DUV exposure cannot resolve a dense pattern at the required pitch, multi-patterning divides that pattern among multiple exposures. The combined sequence can produce finer patterning than a single DUV exposure.
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This is a real way to avoid EUV on a layer when the design, process window, and manufacturing economics allow it. But more exposures mean more masks and process steps, and the full chip still uses a mix of lithography techniques: ASML describes EUV as printing the most intricate layers and DUV systems as printing other layers in the same process.
What ASML’s modeled comparison says
In its 2025 annual-report account of the imec.netzero model, ASML reports that single-patterning EUV uses about 20% fewer process steps per wafer than DUV multi-patterning. The same modeled comparison estimates approximately 10% fewer operational (scope 1 and 2) emissions per wafer for EUV, depending on assumptions. These are model results reported by ASML, not universal production measurements or a complete cost comparison.
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The practical trade-off is therefore not simply “DUV is cheaper” or “EUV is always better.” A process team must weigh whether DUV multi-patterning can meet that layer’s requirements against the added patterning steps, masks, process complexity, and manufacturing considerations. The available figures do not establish an apples-to-apples cost result across all options.
High-NA EUV: a way to simplify EUV patterning, not replace it
High-NA EUV increases numerical aperture from 0.33 to 0.55. ASML describes its 0.33-NA NXE systems as printing highly complex layers in 7 nm, 5 nm, and 3 nm logic nodes, and its 0.55-NA EXE systems as an evolution intended to support further scaling.
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Higher numerical aperture can image finer patterns and may reduce the need for double or triple patterning on some features. That could mean fewer exposures and process steps, but the exposure technology remains EUV. ASML’s 2025 annual-report account of the imec.netzero model reports up to a 30% potential reduction in modeled operational emissions for single-pattern High-NA EUV compared with multi-patterning using 0.33-NA EUV. This comparison is between two EUV approaches; it does not show reduced EUV dependence.
Timing claims should be read as roadmap expectations, not completed deployment. ASML reported that its EXE:5200B shipped in April 2025 and described 2027 as the expected support date for High-NA high-volume manufacturing. The company’s roadmap may change.
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DSA and nanoimprint: promising directions with narrower evidence
Directed self-assembly
DSA uses a material’s self-organizing behavior, guided by a pattern created through lithography, to form additional nanoscale features. The approach has been explored as a way to reduce patterning costs and may complement conventional lithography. A CORDIS project documents development of DSA materials, process models, and computational lithography. That supports describing DSA as a research and process-development route, not as a broadly deployed replacement for EUV in leading-edge logic.
Nanoimprint lithography
NIL transfers a pattern from a mold rather than imaging it through a conventional projection scanner. The 2022 IEEE International Roadmap for Devices and Systems lithography chapter discusses nanoimprint as a technology considered for memory. That is evidence of application interest, not proof of broad production use or a leading-edge logic replacement for EUV.
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Computational lithography improves patterning but does not replace exposure
Computational lithography uses modeling and software to optimize masks, imaging, and patterning processes. It can help address challenges in both EUV and DUV workflows, including multi-patterning. Siemens describes its Calibre EUV tools as supporting EUV modeling and multi-patterning, including challenges associated with High-NA EUV.
Because the software helps design and control a physical patterning process rather than expose the wafer, it is an enabling tool—not an alternative to an EUV or DUV scanner. It may improve the use of a chosen exposure method, but it cannot by itself reduce EUV use on a layer.
How to judge whether an alternative can reduce EUV use
The answer is layer-specific. A process option that works for one pattern or application may not meet the resolution, defect-control, throughput, or manufacturing requirements of another. Compare candidate approaches using criteria such as:
- Layer suitability: Can the method print the specific layer’s patterns at the required dimensions and pitch?
- Exposure and mask count: Does it need several patterning cycles where another approach needs one?
- Process complexity and defect control: Can the full sequence be controlled reliably in manufacturing?
- Throughput and cost: What are the consequences of the complete process flow, rather than just one exposure?
- Manufacturing readiness: Is the method in production for the relevant application, on a roadmap, or still under research?
On the evidence available, DUV multi-patterning is the established route that can displace EUV on selected layers, with added process complexity. DSA and NIL merit attention as possible complementary or specialized approaches, but the cited sources do not establish broad replacement of EUV in leading-edge logic. High-NA EUV may simplify some patterning sequences while continuing to rely on EUV, and computational lithography supports the patterning process rather than replacing the scanner.
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