Flywheel current injection control (FCIC) stabilizes a constant-on-time (COT) buck regulator by creating a feedback ramp from the inductor’s recirculating current. That ramp performs the stabilizing job that output-capacitor equivalent series resistance (ESR) normally performs, so the regulator can use low-ESR ceramic capacitors without depending on their ESR for stability.
Why does a COT regulator need a stabilizing ramp?
A COT buck regulator keeps its switch on for a set time and varies the off-time to regulate the output. During the off-time, the synchronous switch carries the inductor’s recirculating, or “flywheel,” current.
In conventional COT control, the voltage change across the output capacitor’s ESR contributes a ramp to the feedback signal. The control comparator uses that changing signal to determine when to begin the next switching cycle. If the ESR is very low, the ramp may be too small: the comparator can trigger too early, leading to sub-harmonic oscillation and unstable behavior. This dependence makes very-low-ESR capacitors, especially ceramics, a design challenge for an ESR-stabilized COT regulator.
How does flywheel current injection control work?
FCIC senses a waveform related to the flywheel current and injects it into the feedback reference through a controlled resistance. The injected signal supplies a designed ramp for the comparator, rather than relying on the output capacitor’s ESR to create one.
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The practical change is where the stabilizing behavior comes from: an uncontrolled capacitor ESR is replaced by a designed sensing resistance or, in an implementation that uses it, the synchronous switch’s resistance. With the ramp no longer dependent on capacitor ESR, a designer can use low-ESR ceramic output capacitors while maintaining the control signal needed for stable operation.
What performance did the FCIC example report?
A technical article by National Semiconductor authors Lawrence H. S. Ling, Issac Hsu and Gladis Koon, published approximately in 2007, describes an FCIC COT buck example with a 4.5–36 V input range and 93% maximum efficiency. The article also reports output ripple below 5 mV with ceramic output capacitance.
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The stated example conditions were an 18 V input, 3.3 V output, two 47 µF output capacitors and a 1 MHz switching frequency. The 93% figure is a reported maximum, and the sub-5 mV ripple result belongs to that article’s ceramic-capacitor example; neither should be read as a guaranteed result for other controllers, component choices or operating conditions. The article does not provide a full modern-controller datasheet, statistical tolerance analysis, thermal test protocol or independent replication.
The same article reports a 200 mA step-load measurement in its discussion of the minimum-ESR stability criterion for conventional COT control. That measurement is not, by itself, an apples-to-apples transient comparison of FCIC against conventional COT.
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How does FCIC compare with other COT approaches?
The approaches differ in how they obtain the control ramp. The available reports do not establish a common test setup across them, so unreported metrics should not be treated as equal or inferred from results for another architecture.
| Comparison point | Conventional ESR-stabilized COT | FCIC | Internally ramp-compensated COT |
|---|---|---|---|
| Source and evidence | National Semiconductor article, approximately 2007 | National Semiconductor article, approximately 2007 | IET Power Electronics study, 2020 |
| Low-ESR stability | Depends on sufficient output-capacitor ESR; the article discusses a minimum-ESR stability criterion. | Injects a flywheel-current-related ramp to avoid relying on capacitor ESR. | Uses internal ramp compensation; the study does not establish equivalence to FCIC. |
| Output ripple | not stated (National Semiconductor article) | Below 5 mV in the reported ceramic-capacitor example; conditions are given above. | not stated (IET Power Electronics study) |
| Transient response | not stated (National Semiconductor article) | not stated as a direct FCIC result (National Semiconductor article) | Described as fast for point-of-load applications; no directly comparable FCIC test is established (IET Power Electronics study). |
| Regulation accuracy | not stated (National Semiconductor article) | not stated (National Semiconductor article) | ±0.5% target regulation accuracy reported for the study’s adaptive COT scheme (IET Power Electronics study). |
| Efficiency | not stated (National Semiconductor article) | 93% maximum reported; not an independently replicated comparison. | not stated (IET Power Electronics study) |
| Switching-frequency variation | not stated (National Semiconductor article) | not stated (National Semiconductor article) | not stated (IET Power Electronics study) |
| Capacitor size and profile | Needs ESR suitable for stability; specific size and profile not stated (National Semiconductor article). | Example uses two 47 µF ceramic output capacitors; voltage rating, dielectric, package and DC-bias derating must be checked for a selected part (National Semiconductor article). | not stated (IET Power Electronics study) |
| Sensing-resistance tolerance | Not applicable to the ESR-ramp mechanism as described. | not stated (National Semiconductor article) | not stated (IET Power Electronics study) |
| Implementation complexity | Relies on capacitor ESR to supply the ramp; implementation detail not quantified (National Semiconductor article). | Uses designed current sensing and injection; implementation complexity is not quantified (National Semiconductor article). | Uses internal ramp compensation; implementation complexity is not quantified (IET Power Electronics study). |
A 2015 Alpha & Omega Semiconductor patent application describes a related AC-injection COT buck method: it combines divided load voltage with a positive/negative triangular periodic signal and compares the sum with a target to control the switches. It addresses unstable output voltage and capacitor-ESR control challenges, but the description does not establish that this method is identical to National Semiconductor’s FCIC.
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Analog Devices groups COT, hysteretic control and pulse-frequency modulation among primary regulator control schemes. That broader classification helps place COT in the control-method landscape, but it does not provide a direct performance comparison for FCIC.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What should a designer verify before using FCIC?
- Confirm the controller’s actual implementation. FCIC is a controller-level control technique, not a property of every COT regulator or buck module. Verify the controller documentation before treating a product as FCIC-based.
- Check the capacitor in the intended circuit. The cited example uses two 47 µF low-ESR ceramic capacitors. For a real part, verify voltage rating, dielectric, package, capacitance after DC-bias derating and ripple-current rating; the nominal capacitance alone is not enough.
- Check sensing and operating limits. The stability contribution depends on the designed sensing resistance or synchronous-switch resistance. Validate tolerances and operating conditions against the chosen controller’s documentation; the 2007 article does not provide a full modern tolerance analysis.
- Validate the whole power stage. Output ripple and transient response depend on the implemented regulator and its components. Treat the article’s example figures as evidence for that reported setup, not as design guarantees.
A generic COT evaluation board can help with initial prototyping, but its availability does not establish that it implements FCIC. Controller-level documentation is needed to verify the topology.
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