Integrate MEMS and IC design as one connected flow, not as a sequence of manually redrawn layouts and separately maintained models. Start with a characterized fabrication process and foundry PDK, build process-aware MEMS geometry and behavioral models, connect those models to system and circuit simulation, then verify the combined implementation against the foundry’s rules and signoff requirements.
What does it mean to bring MEMS into an IC design flow?
MEMS devices have physical geometry and mechanical behavior as well as electrical interfaces. An IC flow, by contrast, is organized around circuit schematics, models, layout, verification and manufacturing data. Integration means keeping those views aligned: the MEMS geometry, its simulated behavior, its electrical connections and the manufacturing constraints must describe the same design.
In a disconnected workflow, teams may pass files between tools, maintain behavioral models separately, or redraw MEMS geometry in an IC layout environment. Those handoffs can cause a model, layout or process assumption to drift from the version used elsewhere. A structured flow reduces that synchronization risk by linking process information, geometry, multiphysics analysis, behavioral models and IC implementation.
Start with the process and foundry enablement
Before choosing a layout tool or building a model library, identify the MEMS fabrication process and confirm that it is characterized for the device you intend to design. The process definition needs to capture the material, geometric and process parameters that determine what can be fabricated. A flow built around a generic process description may help explore a concept, but it cannot establish manufacturability for a particular foundry.
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The foundry’s process design kit (PDK) is a key dependency. GlobalFoundries describes PDK resources as covering process models and rules, libraries, design-rule checking (DRC), layout-versus-schematic (LVS) verification, reference flows, IP integration and signoff support. For a MEMS-plus-IC design, confirm which of those resources apply to the MEMS process, which apply to the electronics, and how the foundry expects the two domains to be combined. Availability and scope are process-specific; a standard IC PDK should not be assumed to include MEMS device models or MEMS layout verification.
Build process-aware MEMS geometry
Capture the device in an environment that understands MEMS geometry and fabrication, rather than treating it as an arbitrary drawing. Reusable, parameterized primitives—such as beams, plates, electrodes and electrostatic drives—make it easier to vary dimensions without rebuilding each structure from scratch. Keep the geometry associated with a fabrication-aware 3D representation so that the layout and the physical structure remain connected.
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Siemens describes L-Edit MEMS as supporting true curve geometry, component libraries, design-rule checking and fabrication-aware 3D solid modeling. Its documented flow also describes using SoftMEMS/MEMS Pro3D for 3D modeling. These are examples of capabilities to evaluate, not a guarantee that any particular foundry process, device library or signoff deck is supported. Check the chosen environment against the actual process documentation and foundry requirements.
Analyze the physical device, then create models for the system
Use the MEMS geometry to investigate the device’s physical behavior before relying on a compact representation in a larger circuit or system. A MEMS-aware design flow should be able to export geometry to multiphysics analysis tools, where mechanical, electrical and coupled-domain behavior can be examined. Siemens lists integrations with Ansys, COMSOL and OnScale for this purpose. The relevant solver and analysis setup depend on the device and the questions being evaluated.
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Next, create behavioral models that can be used at the abstraction levels required by the project. System or algorithm development may need a model usable in an environment such as MATLAB Simulink; analog and mixed-signal design needs a model that can participate in circuit simulation. Coventor’s discussion of MEMS+ describes a structured handoff involving Simulink and Verilog-A, including work with Cadence Virtuoso. That example illustrates how MEMS behavior can be represented for both system-level and circuit-level work; it does not establish that every model or tool version is interchangeable.
Make the model’s assumptions and intended use explicit. A faster, simplified behavioral representation and a model retaining more physical detail serve different purposes. Record which parameters the model exposes, which physical effects it represents, and what analysis supports its use. Do not treat a system-level result as a substitute for multiphysics analysis or foundry verification.
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Connect MEMS and electronics in the IC environment
Once the MEMS model and geometry are established, bring the device into the electronics workflow at the appropriate boundaries: its electrical terminals and model for circuit design, and its physical implementation for layout and verification. Keep the mapping between the MEMS representation and the IC implementation controlled, so changes to device geometry or interfaces are not silently left out of schematics, models or layouts.
Coventor’s MEMS+ example with Cadence Virtuoso and MATLAB Simulink is evidence of one structured tool combination. It should be read as an example rather than a universal plug-in path: the available handoffs depend on the selected software, licenses, model formats and foundry enablement. Siemens likewise describes its L-Edit MEMS flow as supporting integration with analog/mixed-signal circuitry. Confirm the actual import, export and verification steps with the tool vendor and foundry before committing to a flow.
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Choose an integration architecture
The physical partition affects process complexity, performance, packaging and how work is divided between the MEMS and IC teams. The right choice depends on the device, electronics and available manufacturing process; the architecture should be established early enough to inform both modeling and verification.
| Architecture | What it means for the design | Key consideration |
|---|---|---|
| Hybrid multi-chip | MEMS and IC are implemented as separate chips and brought together in the finished system. | Plan the interface and packaging around separate devices; this avoids assuming that the MEMS and electronics share one fabrication process. |
| Wafer-level monolithic | MEMS and electronics are integrated at wafer level within a monolithic approach. | Process compatibility and manufacturing complexity are central constraints; confirm that the foundry supports the required combination. |
| Heterogeneous | Different technologies or components are combined into an integrated design. | Define how the technologies are partitioned and connected, and verify the corresponding process and packaging support. |
These are broad architectural categories, not interchangeable layout options. The foundry’s supported process and integration route determine which choices are viable.
Evaluate a MEMS-to-IC flow before selecting tools
Compare candidate flows against the work your design actually needs. A tool’s ability to draw MEMS geometry is not enough if the flow cannot preserve the geometry-to-model relationship or meet the foundry’s verification requirements.
- Process awareness and portability: Can the flow represent the target process and its design rules? What needs to change to move to another foundry or process?
- Geometry and libraries: Are parameterized structures, reusable components and fabrication-aware 3D views available for the device class?
- Model fidelity and speed: Which physical behaviors and design parameters are represented, and are models available at both system and circuit levels?
- Handoffs and multiphysics interoperability: Can geometry and models move into the required solvers and IC tools without uncontrolled redraws or manual re-entry?
- IC integration and verification: Does the flow connect to the project’s schematic, layout, simulation, DRC, LVS and signoff processes?
- Manufacturing and architecture support: Does the foundry enable the intended hybrid, monolithic or heterogeneous implementation?
A practical sequence for implementation
- Confirm the manufacturing target. Identify the MEMS process, its characterized parameters and the foundry’s supported integration architecture.
- Obtain the relevant PDK and reference flow. Establish which rules, models, libraries, verification decks and signoff data cover the MEMS device and the associated electronics.
- Create or select parameterized MEMS primitives. Maintain the geometry, process assumptions and 3D representation together.
- Analyze the physical structure. Export to an appropriate multiphysics solver for mechanical, electrical or coupled-domain analysis.
- Generate level-appropriate behavioral models. Provide the representations needed for system simulation and analog/mixed-signal circuit simulation, documenting their assumptions and limitations.
- Integrate with IC design and layout. Connect the model and electrical interface to the circuit flow, and keep the physical implementation consistent with the MEMS geometry.
- Run foundry verification and prepare signoff. Use the applicable DRC, LVS, reference-flow and signoff resources; resolve gaps with the foundry rather than assuming a generic MEMS model or rule set is sufficient.
Why this matters beyond tool choice
Coventor authors Stephen Breit and Joost van Kuijk argued that bringing MEMS design into the IC mainstream could reduce design costs, shorten time to market and make MEMS design less confined to specialist teams inside integrated device manufacturers. The practical implication is broader than adopting one EDA product: a repeatable flow makes device knowledge, models and verification usable across the MEMS, circuit and manufacturing teams.
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