Positive logic treats a HIGH voltage as logic 1 and a LOW voltage as logic 0. Negative logic reverses that interpretation: HIGH is 0 and LOW is 1. The voltage itself does not change; only the convention used to describe it changes. That distinction also explains why a circuit described as NAND in positive logic can be described as NOR in negative logic.
Positive and negative logic compared
| Convention | HIGH voltage means | LOW voltage means | Asserted level |
|---|---|---|---|
| Positive logic | 1, true, or asserted | 0, false, or deasserted | HIGH (active-high) |
| Negative logic | 0, false, or deasserted | 1, true, or asserted | LOW (active-low) |
These labels describe how a circuit’s electrical levels are interpreted as Boolean values. The circuit family and interface determine what voltage counts as HIGH or LOW; the logic convention determines which Boolean value each level represents. The University of Texas digital-logic chapter describes positive logic as treating the presence of voltage as “1,” true, asserted, or high: Digital Logic.
What active-high and active-low mean
“Active” means that a signal is asserted or performing its intended control function. An active-high signal performs that function when HIGH; an active-low signal performs it when LOW. Thus, an active-low reset is asserted at LOW—not because LOW always means ON, but because the reset signal’s defined polarity makes LOW its asserted level.
Reset, chip-select, enable, and interrupt signals can be active-low. Read the signal’s polarity marking rather than assuming that a logic 0 is always inactive. In the terminology used by Muhammad H. Rashid’s Fundamentals of Digital Logic and Microcomputer Design, positive logic and active-high logic correspond: HIGH = 1 and LOW = 0. Textbook information.
Why NAND can be called NOR in negative logic
Consider a two-input device whose output is LOW only when both inputs are HIGH. In positive logic, HIGH is 1 and LOW is 0, so the output is 0 only when both inputs are 1. That is the NAND truth table.
| Electrical inputs | Electrical output | Positive-logic values (A, B → Y) | Negative-logic values (A, B → Y) |
|---|---|---|---|
| LOW, LOW | HIGH | 0, 0 → 1 | 1, 1 → 0 |
| LOW, HIGH | HIGH | 0, 1 → 1 | 1, 0 → 0 |
| HIGH, LOW | HIGH | 1, 0 → 1 | 0, 1 → 0 |
| HIGH, HIGH | LOW | 1, 1 → 0 | 0, 0 → 1 |
When the voltage labels are reversed, the same behavior produces a NOR truth table: the output is 1 only when both negative-logic inputs are 0. The silicon has not changed. This is a consequence of complementing the interpretation of the inputs and output, a Boolean duality described in Rashid’s textbook.
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How to read polarity markings
Signal names and schematic symbols help distinguish an asserted state from a voltage level. A suffix such as _N (for example, RESET_N), a slash or overbar, or an inversion bubble can indicate an active-low signal. Conventions vary by document, so check the schematic legend or datasheet rather than relying on a name alone. Rashid’s textbook discusses polarity notation, while the University of Texas digital-logic chapter explains the underlying voltage-to-logic interpretation.
- For an active-high signal, HIGH asserts the function.
- For an active-low signal, LOW asserts the function.
- When connecting devices, confirm that one side’s asserted level matches the other side’s expected polarity; if not, the interface may need an inversion.
Keep voltage, logic value, and function separate
To interpret a signal reliably, identify three things: its measured electrical level (HIGH or LOW), the chosen logic convention (which maps that level to 1 or 0), and the signal’s function (which level asserts it). Keeping those separate prevents the common mistake of treating “LOW,” “0,” and “off” as interchangeable.
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