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Siemens Tessent AnalogTest is enterprise software that automates design-for-test circuitry and digital test-pattern generation for analog and mixed-signal ICs. Siemens says it can cut pattern-generation work from months to days and run generated tests in under one millisecond on almost any digital tester; those are vendor-reported claims, not independently verified benchmarks.

What Tessent AnalogTest is—and what it automates

Announced by Siemens Digital Industries Software on September 16, 2025, Tessent AnalogTest is an electronic-design-automation (EDA) tool for chip development and production test. It is not a standalone consumer tester or a general-purpose instrument.

The software automates two linked tasks: generating low-impact design-for-test (DFT) circuitry for analog blocks, and generating digital test patterns to exercise that circuitry. Siemens describes the solution as suitable for nearly any analog circuit block. Its purpose is to make analog defects more testable through digital test infrastructure, rather than relying only on conventional specification-based analog tests.

How the workflow uses digital test infrastructure

AnalogTest combines access mechanisms, test generation and defect simulation. Siemens describes using high-level Instrument Connectivity Language (ICL) and Procedural Description Language (PDL) test descriptions associated with IEEE P1687.2, an analog extension of the digital IJTAG standard. The workflow also uses automated test-pattern generation (ATPG) and Siemens Tessent DefectSim to evaluate defects in simulation.

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  1. Add test access: The flow generates DFT circuitry intended to have minimal impact on the analog design, with digital IJTAG-style access.
  2. Generate patterns: AnalogTest creates digital patterns for testing analog circuitry through that access path.
  3. Assess defect coverage: Tests can be simulated with DefectSim before tape-out to estimate which modeled defects they detect.
  4. Run tests in production: Siemens says the generated tests can run on almost any digital tester, reducing reliance on mixed-signal ATE for the covered tests.

“Digital-only tester” does not mean that the device under test contains no analog behavior, or that all analog characterization and parametric measurement disappear. The claim is that generated digital patterns can test targeted analog circuitry using digital ATE. Siemens also identifies algorithmic trimming and top-up parametric tests as supported use cases; the announcement does not say these needs are eliminated.

How much faster—and what coverage does Siemens report?

Siemens and onsemi have published several performance figures, but they describe different parts of the flow and use different comparison points. Treat them as attributed claims, not as a single independently verified benchmark.

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Claim What it refers to Attribution and qualification
From months to days Analog test-pattern generation Siemens, in its September 2025 announcement; no independent measurement details are provided.
Up to 100 times faster Testing analog circuitry compared with traditional manual methods Siemens, in its September 2025 announcement; the wording is “up to,” not a guaranteed result for every design.
Less than one millisecond Execution time for generated tests on “almost any digital tester” Siemens, in its September 2025 announcement; no tester models or per-design conditions are stated.
Up to 1,000 times faster Simulation-based defect-coverage verification compared with specification-based tests Siemens, in its September 2025 announcement; this is a simulation comparison, not a claim about production test execution.
Greater than 95% analog defect coverage; better than 100 times test-time improvement Results on a taped-out design Reported by onsemi and quoted by Siemens in September 2025; the announcement does not supply independent validation or detailed test conditions.
10×–100× reduction in silicon analog test time Compared with traditional specification tests Siemens’ product-page claim as described in the available materials; it is a vendor claim, and specific design conditions are not stated.

These figures are useful as targets to investigate in a product evaluation, not as a substitute for measuring a specific design. Results can depend on the block, chosen defect models, DFT impact, coverage target and tester setup; the cited claims do not provide a controlled cross-vendor comparison.

Where DefectSim, IJTAG and functional safety fit

Tessent DefectSim

DefectSim is the simulation component Siemens pairs with AnalogTest. Siemens’ DefectSim datasheet describes transistor-level fault simulation for analog, mixed-signal and non-scan digital circuits, including realistic shorts, opens, variations and user-defined defects. That lets teams evaluate coverage against modeled faults and examine quality-related test questions before manufacturing. The quality of any coverage estimate depends on the defect models and assumptions used.

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IEEE P1687.2 and IJTAG

Siemens references IEEE P1687.2 for high-level ICL and PDL test descriptions. The release characterizes P1687.2 as an analog extension of digital IJTAG. The practical goal is to connect analog test structures to a structured digital access and pattern-generation flow; teams should confirm the standard and implementation details relevant to their design and existing infrastructure.

ISO 26262-related use

Siemens says the tests can support ISO 26262 functional-safety metrics. That is not equivalent to a claim that using AnalogTest by itself makes a product compliant or supplies all required safety evidence. Safety teams still need to establish that the methods, fault models, coverage results and documentation meet the requirements applicable to their product.

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Who should evaluate AnalogTest?

The most relevant users are semiconductor design and test teams with analog or mixed-signal blocks that want structured DFT, digital ATPG and pre-silicon defect-coverage analysis. It may be worth evaluating when a team is trying to reduce dependence on mixed-signal test resources, shorten test-development work, or improve analog defect coverage within an established Tessent and digital-ATE workflow.

  • Potential fit: Teams able to add and validate DFT circuitry in their analog designs and integrate the generated patterns into production test.
  • Key evaluation question: Does the proposed DFT preserve acceptable analog behavior while detecting the defects that matter for this product?
  • Workflow question: How does the tool integrate with the team’s existing IJTAG, ATPG, simulation, tester and EDA flows?
  • Evidence question: Which defect models, coverage metrics and test-time measurements will Siemens demonstrate on a representative block?
  • Safety question: What artifacts and validation steps are needed for the team’s ISO 26262 process?

Availability, pricing and what to confirm

At announcement on September 16, 2025, Siemens said early partners were using Tessent AnalogTest and planned general availability for December 2025. The available product information does not establish whether availability, regional access or licensing terms have since changed. Siemens has not published a price, licensing metric or deployment scale in the cited materials, so prospective users should confirm current availability, commercial terms and product requirements directly with Siemens.

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