To implement PCI Express (PCIe) in an FPGA, first choose a device and vendor IP that support the required link and port role, then decide how application logic will exchange data, and finally validate the generated design from link training through host-visible transactions. Most supported FPGA families provide hardened PCIe protocol logic; you generally integrate that IP rather than build the entire PCIe stack yourself. The exact options and interfaces depend on the FPGA family, IP revision, board, and tool flow.
What the PCIe IP does—and what your logic still must do
PCIe is a layered, packet-based protocol. AMD’s 7 Series integrated block documentation describes Physical, Data Link, and Transaction layers; Intel’s GTS PCIe guide likewise describes hardened transaction, data-link, and physical layers. The hard IP handles protocol functions, while an interface connects it to application logic. This division reduces the protocol machinery you must implement directly, but it does not remove the need to integrate clocks, resets, configuration, application behavior, and software.
The user-facing interface is vendor- and IP-specific. For example, AMD PG054 exposes AXI4-Stream for transaction traffic as well as system, PCIe, configuration, and physical-layer control/status interfaces. Intel’s cited GTS architecture uses soft fabric logic to adapt user logic to its hard IP. Do not assume an AXI interface, clocking model, or signal set from one family applies to another.
Choose the port role before choosing an example design
Endpoint
An endpoint is discovered and configured by a host or root complex. This is the usual architecture when an FPGA card is installed in a computer and the computer’s host software communicates with it. Your design must expose the device behavior and transactions expected by the host-side software.
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Root port
A root port lets the FPGA participate in the root complex and communicate with downstream PCIe endpoints. AMD’s overview describes attaching devices such as Ethernet controllers, Fibre Channel HBAs, and NVMe SSDs. This role changes the system topology and software assumptions; it is not simply an endpoint design with different settings. AMD documents endpoint and root-port configurations for the 7 Series integrated block, but availability in other families must be checked in their specific guides.
Match the FPGA family and IP to the required link
A PCIe generation or lane-width headline is not a guarantee for every FPGA in a vendor’s catalog. Confirm the exact part, IP variant, tool/IP revision, and board routing before settling on an architecture. AMD explicitly directs users to the applicable product guide for supported link widths and rates.
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| Documented device or IP scope | Documented PCIe capability | How to interpret it |
|---|---|---|
| AMD 7 Series integrated block, PG054 v3.3, released 2024-12-06 | 2.5 Gb/s and 5.0 Gb/s endpoint and root-port configurations; lane choices from x1 through x8 depending on IP variant and interface width. | These are PG054’s 7 Series configurations, not a general specification for AMD FPGAs. The guide points to the separate Virtex-7 PG023 guide for Gen3 support. |
| AMD Versal PCIe blocks, per AMD’s PCI Express technology overview accessed in 2026 | Some cited blocks support up to 32 GT/s per lane with eight lanes; some support up to 16 GT/s per lane with sixteen lanes. | These are block-specific maxima, not a promise that every Versal part or configuration supports either maximum. Consult the guide for the target block. |
| Intel Agilex 3 GTS, version 25.1 guide | PCIe 3.0 x4. | Applies to the cited Agilex 3 GTS documentation. |
| Intel Agilex 5 GTS, version 25.1 guide | PCIe 4.0 x8 on performance-oriented D-Series, or x4 on power-oriented E-Series. The cited guide says the D-Series x8 configuration can be configured as two independent x4 links. | Check the precise device and configuration; these figures are not interchangeable across Agilex 5 variants. |
Rates and widths describe link capabilities, not application payload throughput. Effective data transfer also depends on the configured link, transaction pattern, protocol overhead, application logic, and software. Do not treat a per-lane signaling figure as a guaranteed user-data rate.
Decide how application logic will move data
Transaction interface for control or custom behavior
For a modest register/control interface or a custom transaction scheme, application logic can connect to the transaction-facing interface documented for the selected IP. The design must still implement the required application behavior and handle that interface’s protocol, flow control, and clock/reset requirements as specified by the vendor guide.
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DMA or bridge for sustained transfers
For sustained host-to-device or device-to-host data movement, evaluate a DMA subsystem or bridge rather than assuming a simple custom interface is sufficient. AMD’s overview identifies XDMA and QDMA subsystems and partner offerings such as AXI Bridge with DMA for PCIe. It characterizes QDMA as queue-based; the overview also describes bridge functionality. Intel’s 2024 AXI Streaming PCIe guide discusses optional adapters or blocks for DMA and scalable-switch use cases.
These names do not imply that every device includes the same feature or software path. Before selecting a block, verify target-part support, licensing, driver availability and compatibility, software interface, current support status, and whether its transfer model fits the application. Optional integrated functions and soft-IP subsystem choices vary by architecture.
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Implement from the vendor design example
A generated example design and its testbench provide a practical starting point for understanding the selected IP’s ports, configuration, and integration flow. AMD PG054 calls using the existing PCIe example design the simplest method when it fits the project. Intel’s GTS guide outlines generation, interface connection, simulation, compilation, driver setup, and running an example.
- Confirm the target and constraints. Check the exact FPGA part and IP revision for port role, generation, lane width, interface, transceiver and pin requirements, and board support. Confirm that the board routes the required PCIe lanes and reference clock and provides an appropriate connector and power/configuration setup.
- Generate the vendor IP and example design. Use the device-specific flow and settings in the current product guide. Treat the example as a reference for that IP configuration, not as a universal design template.
- Simulate the IP-to-application connection. Start with the supplied testbench or simulation flow, then exercise the application behavior you add. Simulation can expose interface integration errors before hardware bring-up; it does not establish that the physical link or host software will work.
- Integrate application logic, clocks, resets, and configuration. Follow the selected guide’s clock and reset requirements and make the host-visible configuration match the intended device behavior. For the PG054 workflow, AMD describes replacing the PIO example with the user application. Its guide also notes preserving relevant SPI/BPI settings from the bitstream Tcl flow where applicable.
- Compile and implement the design. Resolve timing, resource, pin, and transceiver constraints using the target device’s tool flow. Successful compilation alone does not show that the link will train or the host will enumerate the device.
- Bring up the hardware and validate in stages. Check FPGA configuration readiness and board power, then verify link training and host enumeration. After the host can discover the device, validate the intended transactions using the actual application and driver.
Make enumeration a deliberate milestone
Link bring-up depends on more than RTL. FPGA configuration readiness, reset and clock integration, board power, and host behavior all affect whether and when the host can access an endpoint. AMD PG054 has dedicated configuration guidance and discusses configuration access timing, board power in real systems, and FPGA configuration methods in relation to PCI-SIG requirements.
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If enumeration does not occur, separate the investigation into stages rather than debugging application traffic first: establish that the FPGA has configured and is ready, check board-level power and clock/reset integration against the target guide, then investigate link training and host discovery. Once enumerated, move on to configuration and transaction behavior. Standards-level compliance details belong to the relevant PCI-SIG specification; vendor summaries are not a substitute for reviewing that specification when the design requires compliance assurance.
Compare complete implementations, not just the maximum link
Before committing to an FPGA, board, or IP option, compare the factors that affect the whole system:
- Supported PCIe generation, lane width, and any reduced-width configurations for the exact part and IP.
- Endpoint, root-port, or other port-role support relevant to the topology.
- Hard-IP responsibilities, fabric adapters, application interface, and clock/reset integration.
- DMA or bridge availability, licensing, driver requirements, and software interface.
- Device resources and power, plus board connector, lane routing, transceivers, reference clocks, and configuration method.
- Tool and IP revision, design-example availability, and the documentation applicable to the target.
Evaluation kits can help validate a design against a specific device family, but a board name alone is not a compatibility check. AMD’s overview names the Artix 7 AC701 and Kintex 7 KC705 as PCIe evaluation-kit examples. Confirm the kit’s supported generation and lane width, connector and routing, clocking, transceivers, tool-version support, and availability for your intended work.
Use the device-specific guide as the implementation authority
AMD PG054 v3.3 is a bounded reference for 7 Series, with a release date of 2024-12-06; AMD’s broader PCI Express technology overview was accessed in 2026. Intel’s cited GTS guide is version 25.1, while its AXI Streaming PCIe guide is dated 2024-04-12. Tool versions, IP capabilities, licensing, and board availability can change. Select the guide for the exact device and IP revision, and use the PCI-SIG specification for standards-level requirements.
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