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Lockstep architecture primarily enhances an MCU’s ability to detect certain processor faults; it does not inherently make a program run faster. Two processor channels execute the same instructions, and hardware checks whether their behavior matches. That redundancy supports safety-related designs, while reducing the processing capacity available for separate work unless the MCU also has independent cores.
How lockstep works
A lockstep design pairs a main processor with a checker processor. Both run the same program flow, and a comparator checks that their behavior agrees. If it detects a mismatch, the MCU can report or react to the discrepancy according to its implementation.
For example, Microchip documentation says its two identical CPUs execute the same program flow and that a mismatch triggers a Machine Check Reset; its comparator is outside the main CPU. Arm’s Cortex-M23 application note likewise describes two processor instances executing identical code in tandem and checking whether their outputs are equivalent.
The comparison boundary is device-specific. Lockstep does not automatically mean every peripheral, memory path, or other system element is duplicated. ST’s SPC58 reference manual describes replicated safety-relevant processing elements that behave as one core from the software perspective. Its SPC57 K line, by contrast, illustrates a main core in lockstep with a checker alongside a separate I/O core.
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What lockstep changes about performance
It spends redundant compute on checking
The checker repeats the main processor’s work rather than executing a separate application thread. Lockstep’s direct benefit is therefore fault detection and support for safety-related system design, not general acceleration of an individual program. Compared with split operation, using processors in lockstep can leave fewer resources for independent computation; the actual throughput tradeoff depends on the device and workload.
A specific non-MCU comparison illustrates why figures must be kept in context: AMD’s WP565, released December 18, 2025, reports up to 200k DMIPS in split mode and up to 100k DMIPS when all clusters are configured in lockstep for its described eight-core Cortex-A78AE arrangement. This is not an MCU benchmark or a universal two-to-one lockstep penalty.
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Independent cores can preserve system-level compute
Some designs pair checked processing with independent cores that can handle other work. ST describes an arrangement with a lockstep processing core and an I/O processor core for distinct computational and peripheral tasks. Renesas describes the RH850/U2A as having up to four 400 MHz CPU cores in a dual-core lockstep structure. Such arrangements can provide compute capacity beyond the lockstep pair, but do not change the fact that the paired processors repeat work.
Vendor claims are design-specific
Texas Instruments says its Hercules architecture can provide safety response “without any additional performance impact.” Treat that as a claim about TI’s design, not a general property of lockstep. A design’s response time and throughput depend on how its safety mechanisms are implemented and on the workload being run.
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How to evaluate lockstep in an MCU
When comparing MCUs or operating modes, focus on the architecture and the intended workload rather than assuming that “dual core” means twice the application performance. Check:
- Independent compute: How many cores remain available to run separate tasks in the selected mode?
- Comparison boundary: Which processors and other system elements are included in the lockstep checks?
- Mismatch response: How does the device report a discrepancy, and what action does it take?
- Safety evidence: What safety use cases does the vendor support, and what documentation is available for the specific device?
- Workload performance: What throughput does the MCU deliver on the intended application in the selected mode?
The cited vendor material does not establish comparable workload benchmarks across product families, so figures from different architectures should not be used to rank them directly.
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