Do these 3 things before closing this tab:
1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errorsA hybrid prototype keeps the host workstation and FPGA prototype connected by PCIe over Cabling, while a separate transaction-level interface joins the FPGA design to a SystemC/TLM virtual platform. In the historical Synopsys UMRBus-on-HAPS arrangement, this lets a team run whichever blocks are ready as virtual models, FPGA RTL, or physical interfaces instead of waiting for the entire SoC to reach the same implementation stage. The result is a coordinated validation environment—not a generic PCIe cable connecting every component.
What the platform actually connects
The arrangement described by Troy Scott for Synopsys uses UMRBus infrastructure on a HAPS FPGA-based prototyping system. It has three related paths:
- Host-to-prototype path: PCIe over Cabling provides the higher-bandwidth physical connection between a workstation and the FPGA prototype.
- Prototype interface layer: UMRBus supplies hardware infrastructure, operating-system device drivers, APIs and independently addressable interfaces for communicating with logic in the prototype.
- Virtual-to-hardware path: A transaction-level interface connects the FPGA implementation to a SystemC/TLM virtual prototype, allowing transactions to cross between modeled and physical blocks.
Host software can therefore steer the prototype, transfer data, observe completion and control experiments through the supported driver and API stack. The cable is the host link; it is not itself the transaction-level connection between the virtual platform and FPGA logic. The original architecture is documented in the 2013 Embedded.com article by Troy Scott of Synopsys.
Why combine a virtual platform with FPGA hardware?
Use models when RTL or physical IP is not ready
A virtual processor subsystem can stand in for a processor or other IP that is unavailable in RTL or cannot yet be placed on the FPGA. Software can begin running against the model while physical peripherals or accelerators are implemented in FPGA logic.
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Use FPGA logic where throughput or real I/O matters
Existing RTL can be mapped to the prototype when cycle-level behavior, higher execution speed than a pure model, or interaction with real interfaces is important. The virtual side can continue to provide blocks that are expensive, immature or unnecessary to implement physically.
Replace blocks incrementally
A project can begin as a virtual SoC and replace individual subsystems with RTL-based FPGA implementations as they become available. This avoids a single all-or-nothing handoff from simulation to hardware, but it requires stable transaction definitions and disciplined ownership of timing, resets, interrupts and address maps.
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Useful partitioning patterns
| Pattern | Virtual side | FPGA side | Why it is useful |
|---|---|---|---|
| Virtual processor plus physical peripherals | Processor subsystem and software execution | Peripherals needing high throughput or real-world I/O | Exercises firmware against interfaces that are difficult to model faithfully. |
| Legacy or commercial IP bring-up | Virtual model or user application around the IP | Available legacy or licensed RTL | Combines what is already available without waiting for a uniform implementation. |
| Progressive SoC replacement | Unfinished subsystems | Subsystems whose RTL has been verified enough for FPGA implementation | Allows software and system integration to continue while the partition changes. |
| Host-controlled validation | Transaction generation, orchestration and analysis | Design under test and physical interfaces | Supports repeatable transfers, control operations and completion notification from a workstation application. |
What the host link adds beyond JTAG
JTAG remains useful for programming, inspection and occasional debug access. Scott summarized the distinction as: “JTAG is an excellent vehicle for occasional data access, but it was not designed for high-bandwidth communication.” The PCIe-over-Cabling path is intended for applications that repeatedly exchange data with, configure or control the running prototype. That does not make it a universal performance guarantee: achievable rates depend on the specific HAPS generation, interface kit, design, driver and host software.
Validation work this arrangement enables
- Software-driven peripheral tests: a host application can issue commands, move payloads and wait for completion while the FPGA executes the hardware path.
- Firmware development before full RTL completion: a virtual processor or subsystem can execute code while FPGA-based devices expose the interfaces that software must eventually use.
- Real-I/O and protocol checks: physical daughter boards and FPGA logic can interact with external signals while the virtual side supplies the rest of the system.
- Incremental integration: teams can swap a transaction-level model for an RTL implementation and compare system behavior at each replacement.
- Boot-ROM update workflows: the prototype can expose a programmable interface so developers can change boot-ROM contents during bring-up rather than rebuilding the entire platform for every firmware revision.
These activities are strongest when the transaction interface defines clear ownership for data formats, addressability, interrupts, reset sequencing and error reporting. A hybrid setup adds integration work across the virtual platform, FPGA build, host application and physical interface.
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The historical USB 3.0 demonstration
The source article reports a case-specific USB 3.0 demonstration built with HAPS-62, a USB PHY interface daughter board and a UMRBus interface kit. A Windows 7 laptop ran the virtual platform and connected through a USB 3.0 host port; Windows detected the prototype as a volume. DiskBench reported the following application-level values:
| Measurement | Reported result | Qualification |
|---|---|---|
| Read | 0.515 MByte/sec | USB3-Read application benchmark on the described Windows 7 system; not PCIe throughput. |
| Write | 0.500 MByte/sec | USB3-Write application benchmark on the described Windows 7 system; not a general HAPS guarantee. |
| Platform preparation | 3–5 days, plus one day troubleshooting | Effort reported for that case, not a planning promise for other designs. |
| Bring-up schedule | Less than two weeks | The article associates this with expert users of Virtualizer and HAPS. |
Those figures describe the 2013 demonstration and its USB application path. They should not be relabeled as PCIe link speed, extrapolated to another operating system, or used as a current product benchmark. See the complete source article for the original setup description.
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Capacity figures reported for UMRBus
The same article states that one motherboard can provide 27 independent interfaces and that a chain can provide 63 independently addressable interfaces. It also says an 8-bit configuration at a 100 MHz global system clock can reach 800 Mbit/s. These are specifications stated in that historical article, not independently revalidated characteristics of currently sold hardware. Treat the interface count and rate as design-context figures until the vendor confirms them for the exact system generation and kit.
A practical integration sequence
- Freeze the partition contract. Define which components are SystemC/TLM models, which are FPGA RTL and which external interfaces are real. Record transaction payloads, address ranges, interrupts, reset behavior and completion semantics.
- Verify the hardware combination. Match the HAPS generation, PCIe-over-Cabling kit, UMRBus hardware, daughter boards, connectors and required FPGA resources. Do not assume a generic PCIe cable provides the required electrical or protocol compatibility.
- Build and load the FPGA design. Implement the selected RTL, UMRBus interfaces and physical-interface logic, then use the supported programming and debug flow to load the prototype.
- Install the host software stack. Install the vendor driver, API and host application components for the supported operating system. Confirm that the prototype enumerates before debugging application traffic.
- Connect the virtual platform. Attach the SystemC/TLM model through the transaction-level interface and establish clocks, reset release and address-map agreement with the FPGA side.
- Run a minimal transfer test. Start with a short payload and an explicit completion or error response. Check that host, virtual model and FPGA observe identical transaction ordering and status.
- Scale to system validation. Add realistic traffic, firmware, external I/O and fault cases only after the basic path is deterministic. Capture host logs, virtual-platform traces and FPGA status together so a failure can be assigned to the correct layer.
Virtual-only, FPGA-only or hybrid?
| Decision factor | Virtual-only | FPGA-only | Hybrid |
|---|---|---|---|
| Available assets | Transaction-level models and software-facing abstractions | Verified RTL and physical IP | Models, RTL and physical interfaces can coexist |
| Execution need | Fast architectural exploration and broad controllability | Higher hardware fidelity and real-I/O behavior | Assign each block according to fidelity and throughput needs |
| Partition stability | Simple while the model boundary is stable | Simple after RTL integration is complete | Requires transaction contracts that tolerate incremental replacement |
| Host interaction | Depends on the virtual-platform tooling | Depends on the board’s host interface and drivers | Requires coordinated virtual-platform, UMRBus and host API support |
| Integration burden | Mostly model and software integration | Mostly RTL, timing, board and I/O integration | Cross-layer debug and exact hardware compatibility are additional work |
Hybrid is therefore a fit when the project has a mixed readiness profile or needs both modeled flexibility and physical execution. It is not automatically superior: every boundary introduces synchronization, tooling and failure modes that a single-domain prototype would avoid.
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Current context and compatibility limits
Synopsys’ current article on hybrid IP prototyping kits describes connecting a hybrid setup to a host PC with a PCIe cable through a PCIe-4_MGB kit and mounting a PHY daughter board on HAPS-DX7. That demonstrates that PCIe cabling remains part of a vendor-described hybrid workflow, but it does not establish that HAPS-DX7, its kit or its cabling is interchangeable with the historical HAPS-62/UMRBus arrangement.
Other vendors document related PCIe uses that should not be conflated with this transaction-level architecture:
- AMD/Xilinx documents Xilinx Virtual Cable debug over PCIe, involving host software, a driver and an FPGA design component, in its UltraScale Gen3 PCIe guide.
- Intel’s Open FPGA Stack describes installation and software for an Agilex 7 PCIe Attach development platform in its PCIe Attach documentation.
- Altera’s Agilex 5 documentation describes Configuration via Protocol (CvP), in which FPGA configuration uses a PCIe host link; see the CvP guide.
These are adjacent debug, attach or configuration scenarios. None of them demonstrates a drop-in replacement for the UMRBus/HAPS virtual-platform connection.
Compatibility checklist before committing to hardware
- Exact HAPS or FPGA-system generation and supported FPGA device.
- PCIe-over-Cabling kit model, connector type, cable requirements and host-side adapter.
- UMRBus motherboard, interface kit and daughter-board part numbers.
- Supported host operating systems, driver versions and API packages.
- Required Virtualizer, SystemC/TLM and transaction-level integration support.
- Available interface count, FPGA resource usage, clocking limits and external-I/O requirements.
- Vendor confirmation of current availability, replacement parts and support for the intended configuration.
The historical sources do not establish current HAPS-60/HAPS-62 or UMRBus availability, pricing, retail stock or successor compatibility. Obtain a written compatibility statement for the complete system rather than buying a generic FPGA board or PCIe cable and assuming it will enumerate or expose the required UMRBus interfaces.
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