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Nuclei’s NA900 is a configurable RISC-V CPU soft-IP core whose product certificate identifies systematic capability at ASIL D and hardware safety integrity at ASIL D under the certificate’s stated conditions. The core is delivered as RTL and classified as a Hardware Safety Element out of Context (SEooC), so the certificate applies to the named NA900 IP—not automatically to every customer SoC, vehicle, or complete safety system that uses it.
What Nuclei announced
Nuclei described NA900 as the first RISC-V CPU IP to achieve an ISO 26262 ASIL-D product certificate. RISC-V International Community News repeated that announcement on August 28, 2023. Those statements establish Nuclei’s announcement and its publication date; they do not constitute an independently audited, continuously current comparison of every CPU-IP vendor worldwide.
The certificate identifies Nuclei NA900 Processor V1.0.0-RC1, document revision v1r0. Nuclei says the certification work was completed with exida. The certified item is a licensable processor design for semiconductor integration, not a retail processor board or finished automotive computer.
What the ISO 26262 certificate covers
Systematic capability and hardware integrity
The certificate states that the NA900 development satisfies applicable ISO 26262 design-specification, implementation, verification, and functional-safety-management requirements for the listed parts and guidance. It identifies both ASIL-D systematic capability and ASIL-D hardware safety integrity for the certified product conditions.
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
“Systematic capability” concerns the processes and methods used to prevent systematic faults in the design and its development. “Hardware safety integrity” concerns the hardware architecture, diagnostic behavior, and residual-risk treatment. An ASIL-D label therefore describes specific safety properties and evidence; it is not a general performance rating or a guarantee that an entire vehicle system is ASIL D.
Safety mechanisms named in the certificate
- Dual-Core Lockstep (DCLS): two execution paths operate in lockstep so disagreements can be detected.
- ECC for safety-related SRAMs: error-correcting protection addresses memory faults in the covered memories.
- EDC/parity-based bus I/O protection: coding and parity checks help detect faults on protected interfaces.
These mechanisms support the safety case, but their effectiveness depends on the selected NA900 configuration, connected memories and buses, clocking, fault responses, and the surrounding SoC design.
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
Why “SEooC” matters to chip designers
A Hardware SEooC is developed for a safety context that is not yet fully known. Nuclei supplies NA900 as RTL, which the customer integrates into a safety-related IC and then into a larger electronic control unit or vehicle system. The certificate is consequently evidence about the IP’s documented development and analysis in its defined context, not a blanket approval of an implementation that has not been analyzed.
The NA900 certificate assigns integration responsibility to the user. Its exact warning is: “The FMEDA metric results depend on the configuration of the NA900 Processor.” The customer must adjust the failure-mode, effects, and diagnostic-analysis (FMEDA) data to the actual IP configuration and reevaluate it in the context of the safety-related IC or system.
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
FMEDA targets and their limits
| Metric | Certificate target | How to interpret it |
|---|---|---|
| SPFM (single-point fault metric) | ≥99% | Target reported by the NA900 certificate; not a promise that every configuration reaches it without integration analysis. |
| LFM (latent-fault metric) | ≥90% | Target reported by the NA900 certificate; the customer must adapt and reevaluate the FMEDA. |
These figures belong to the certificate’s analysis and conditions. They should not be copied into a product-level safety case without checking the exact core options, memories, interfaces, diagnostic settings, operating assumptions, and external safety mechanisms used in the customer design.
NA900D versus NA900B
Nuclei’s current NA900 product information distinguishes configurations that make the phrase “ASIL-D CPU” more specific:
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
| Configuration | Hardware safety integrity listed by Nuclei | Important qualifier |
|---|---|---|
| NA900D | ASIL D | Specified in Dual-Core Lockstep (DCLS) mode. |
| NA900B | ASIL B | Hardware safety integrity is listed as ASIL B, not ASIL D. |
The systematic-capability statement and the hardware-integrity statement are separate parts of the safety argument. A design team should therefore identify the exact series, operating mode, and safety documentation rather than treating every NA900 variant as interchangeable.
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Nuclei’s NA900 product brief describes a dual-issue, nine-stage in-order pipeline, configurable instruction and data caches, and configurable local memories. The vendor lists engine control, advanced driver-assistance systems (ADAS), automotive gateways, and lidar among potential applications. These are product specifications and intended use cases; they are not independent benchmark results.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
The architecture and safety package address different questions. Pipeline width, cache choices, memory size, and clock targets affect workload capacity and integration cost. Lockstep, memory ECC, bus protection, fault handling, and the safety manual affect the safety case. Selecting a configuration for one dimension does not establish compliance on the other.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What a customer still has to do
- Freeze the IP configuration. Record the NA900 variant, DCLS or other permitted mode, cache and local-memory options, interfaces, clocks, and safety-related features.
- Obtain the safety package. Use the certificate, safety manual, FMEDA data, assumptions of use, verification evidence, and integration guidance supplied for the licensed release.
- Adapt the FMEDA. Recalculate failure rates and diagnostic coverage for the actual RTL configuration and the memories, buses, wrappers, and protections added in the SoC.
- Analyze the complete IC. Include clock, reset, power, interconnect, software-visible diagnostics, external memories, and fault-containment regions that are outside the CPU IP boundary.
- Build the system safety case. Perform the required hardware and software analyses for the ECU and vehicle item, including architectural metrics, dependent failures, safety mechanisms, and validation evidence.
An integrator can use a certified SEooC to reduce duplicated development and assessment work, but it cannot transfer the IP certificate unchanged to the finished product.
NA900 and the later NA300 announcement
Nuclei later presented a separate NA300 product as certified. NA300 should not be merged with the 2023 NA900 announcement: it is a different processor product and does not change what the original NA900 certificate covered or what Nuclei meant by its “first” claim.
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Toolchain context
Nuclei has also reported support for its RISC-V IP in HighTec’s C/C++ compiler suite and described that compiler as ISO 26262 ASIL-D certified. Compiler certification is evidence about the tool and its qualification claims; it does not certify an NA900-based SoC or replace the processor and system integration analyses.
Quick Recap
How to read the headline accurately
- Accurate: Nuclei announced a product certificate for its configurable NA900 RISC-V CPU IP, with ASIL-D systematic capability and ASIL-D hardware safety integrity under stated conditions.
- Too broad: every NA900 configuration, customer chip, or vehicle using the IP is automatically ASIL D.
- Required qualifier: NA900 is a Hardware SEooC supplied as RTL, and its FMEDA must be adapted and reevaluated for the integrating design.
- Current product nuance: Nuclei lists NA900D as ASIL D in DCLS mode and NA900B as ASIL B hardware safety integrity.
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