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Rowhammer is a physical disturbance effect in DRAM: rapidly activating certain memory rows can disrupt data in neighboring rows, potentially flipping a stored bit even though the affected cell was not directly accessed. A flip is not automatically a security breach, and not every DDR4 or DDR5 system is susceptible. The risk and the effectiveness of protections depend on the specific memory and platform.
How can accessing one part of RAM change data somewhere else?
DRAM stores information in cells arranged in rows. A memory controller activates a row to read or write data. In a Rowhammer scenario, repeatedly activating one or more nearby aggressor rows can disturb the electrical charge in a neighboring victim row. If the disturbance accumulates before the data is refreshed or otherwise corrected, a stored 0 may become 1, or a 1 may become 0.
The important distinction is that the victim cell need not be the location a program directly accessed. The effect depends on factors including activation intensity, the DRAM’s characteristics, refresh behavior, controller protections, system configuration, and operating conditions. Ordinary memory reads do not each flip a bit. Intel describes Rowhammer as a DRAM reliability issue that, if successfully exploited, can affect data integrity, confidentiality, or availability. Intel’s Rowhammer guidance explains the layered protections involved.
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From disturbance to security exploit
A bit flip is first a data-integrity event. It becomes a security exploit only if an attacker can trigger a useful change—for example, in a page-table entry, key, or executable logic—and use the result to gain an advantage. In 2015, Google Project Zero described two working privilege-escalation exploits. One used flips in page-table entries on a tested x86-64 Linux system to obtain read-write access to physical memory. That demonstrates what was possible on the tested hardware and software; it does not show that every computer can be compromised the same way. Project Zero’s 2015 account also cautioned that the number of vulnerable or fixable machines was not known.
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Are DDR4 and DDR5 systems vulnerable?
Research has demonstrated Rowhammer bit flips on particular DDR4 and DDR5 devices, including systems with protections intended to reduce the risk. Those results establish that the effect has not been eliminated across all tested platforms; they do not establish what share of consumer computers is vulnerable. A demonstrated bit flip also does not, by itself, prove a practical end-to-end attack on every system.
DDR4: results on tested AMD Zen platforms
ETH Zurich’s ZenHammer evaluation, associated with USENIX Security 2024, reported flips on 7 of 10 tested Zen 2 DDR4 devices and 6 of 10 tested Zen 3 DDR4 devices, despite deployed Target Row Refresh (TRR) mitigations. The same project page reports a DDR5 device with flips among 10 tested devices. These are counts from the study’s selected hardware and methodology, not estimates of prevalence across all DDR4 or DDR5 memory. ETH Zurich’s ZenHammer project page describes the evaluation.
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DDR5: results from Phoenix
The Phoenix research page reports that researchers tested 15 SK Hynix DDR5 DIMMs manufactured between late 2021 and late 2024. All 15 were vulnerable to one of the two tested patterns, with an average of 4,989 bit flips reported. The researchers also report reproducing a privilege-escalation exploit in an average of 5 minutes 19 seconds. These figures describe those DIMMs and the study’s test conditions, not all DDR5 memory or a typical attack time on an arbitrary computer. The page does not state a publication year for these results; the figures were reported on the ETH Zurich Computer Security Group’s page accessed on October 7, 2026. ETH Zurich’s Phoenix research page provides the study details.
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Rowhammer defenses work at different layers. Some aim to prevent or reduce disturbance; others detect or correct errors after they occur, or make it harder for an attacker to arrange a useful exploit. The mechanisms are not interchangeable. Intel’s guidance summarizes the principle: “No single mitigation completely eliminates Rowhammer risk; instead, protections aim to reduce the likelihood of disturbances and limit the impact of any residual errors.” Intel, “Reducing Exposure to Rowhammer.”
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| Protection | Where it operates and what it does | Evidence and practical limit |
|---|---|---|
| TRR-like DRAM protections | Memory-device mechanisms intended to reduce disturbance by refreshing rows at risk. | ZenHammer reported flips on tested Zen 2 and Zen 3 DDR4 devices despite deployed TRR mitigations; this result is specific to the evaluated systems. ZenHammer |
| Refresh management | DRAM, controller, or platform refresh behavior can increase how often data is refreshed, limiting time for disturbance to accumulate. | Phoenix researchers reported that tripling refresh on their test systems—tREFI approximately 1.3 microseconds—stopped Phoenix from triggering flips in those tests. They measured 8.4% SPEC CPU2017 overhead for that mitigation. These are test-specific results, not a universal setting or guarantee. Phoenix |
| ECC and on-die ECC | Error-correction mechanisms can detect or correct some errors, depending on the implementation and error pattern. They are a resilience layer, not a mechanism that ensures disturbance cannot occur. | Phoenix reports flips despite DDR5 on-die ECC. The ECC.fail presentation reports an end-to-end attack on tested Intel servers using Hynix DDR4 ECC memory; it does not establish the same result for every server platform or ECC scheme. Phoenix; USENIX Security 2025, ECC.fail |
| Controller, firmware, and platform protections | Memory-controller features, platform controls, and firmware settings can support protections such as pTRR, system-level ECC, and refresh management. | Availability and behavior depend on the specific platform and supported settings. Intel describes these as parts of a layered approach. Intel’s guidance |
| Operating-system and operational controls | Operating systems can make it harder for unprivileged software to identify physical memory adjacency. Workload isolation, monitoring, and response can also limit exposure or impact. | These controls do not stop the underlying DRAM disturbance by themselves. Intel notes that obscuring physical adjacency is not sufficient alone. Intel’s guidance |
Does ECC RAM prevent Rowhammer?
No. ECC can detect or correct some memory errors, but it does not prevent every disturbance, and its protection depends on the ECC implementation and the error pattern. The Phoenix study reports bit flips despite DDR5 on-die ECC. Separately, the ECC.fail presentation describes an end-to-end Rowhammer attack on tested Intel servers with Hynix DDR4 ECC memory. Neither result means every ECC system is vulnerable to the same attack; together, they show why ECC should not be treated as a categorical guarantee against Rowhammer. Phoenix; ECC.fail
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What should you do about Rowhammer on an installed computer?
For a specific computer, the useful next step is to establish what protections its system and memory actually support. The available evidence does not make buying generic RAM, ECC memory, or a motherboard a proven consumer fix.
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- Ask the computer or DRAM manufacturer about the exact system. AMD’s response to ZenHammer recommends checking with the DRAM or system manufacturer about susceptibility. AMD bulletin AMD-SB-7021
- Check which mitigations the platform supports. AMD lists ECC-supporting DRAM, refresh rates above 1×, disabling memory burst or postponed refresh, and supported Maximum Activate Count (MAC) capabilities among existing mitigations. These options depend on system support and configuration; do not assume a setting exists or is safe to change on every computer. AMD’s response
- Use manufacturer-supported firmware and configuration guidance. Refresh changes and other protections can have platform-specific behavior and costs. The Phoenix result, for example, measured performance overhead in its own evaluation, not a universal cost. Avoid applying a setting from a study to a different system without manufacturer guidance.
- For managed or higher-risk systems, consider layered operational controls. Workload isolation, monitoring, and response can help limit exposure or impact, but they supplement rather than replace hardware and platform protections. Intel’s guidance
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