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Backside power delivery is a chip architecture that routes power through the back of the silicon wafer instead of sharing the frontside wiring stack with signal connections. Separating the two networks can free frontside routing space and help reduce voltage loss, though the gains depend on the chip design and implementation.
How does backside power delivery work?
A power delivery network supplies active devices with power and reference voltages, commonly called VDD and VSS. In conventional designs, power and signal connections share the frontside back-end-of-line (BEOL) interconnect stack. As power routes approach transistors, they pass through metal and via layers that become narrower and more resistive.
With backside power delivery, the power distribution network is routed on the wafer’s backside, apart from the frontside signal network. In the process flow described by imec, the wafer is thinned, backside metal layers are made, and nano-through-silicon vias (nTSVs) connect that metal toward buried power rails (BPRs) near the devices. Implementations vary; not every design uses the same structures or process sequence. imec explains the architecture, and its account of enabling process steps describes building blocks for a backside network.
What are the benefits?
- More frontside routing room: Moving power routes to the backside can leave more of the frontside BEOL available for signal wiring.
- Potentially lower resistive voltage drop: Backside power lines can be wider and less resistive than fine frontside routes. Lower resistance can reduce IR drop, the voltage lost as current travels through the power path.
These are design goals, not guaranteed results for every chip. The actual effect depends on the implementation and design conditions.
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What do the reported IR-drop figures mean?
Imec reported an imec–Arm simulation presented at IEDM 2019. In that comparison, buried power rails with frontside delivery reduced dynamic IR drop by about 1.7× versus traditional frontside delivery; buried power rails with backside delivery reduced it by 7× versus the same traditional frontside reference. These figures describe that simulation’s comparisons, not universal measured outcomes for products or all backside power designs. Imec’s explanation gives the study context.
How does it differ from conventional power delivery?
| Aspect | Conventional frontside delivery | Backside power delivery |
|---|---|---|
| Power routing location | In the frontside BEOL stack, alongside signal interconnects. | On the wafer backside, connected toward devices through implementation-specific structures. |
| Frontside routing | Power and signal routes share interconnect resources. | Power routing is separated from the frontside signal network, potentially freeing routing space. |
| Device connection | Power travels through frontside metal and via layers toward the transistors. | May use nTSVs and buried power rails; the exact structures vary by implementation. |
| IR-drop evidence | The reference point in the cited imec–Arm simulation. | The same simulation reported lower dynamic IR drop for its buried-rail backside configuration; results are not a universal ranking. |
What is Intel PowerVia?
PowerVia is Intel’s branded implementation of backside power delivery, not a synonym for every backside power architecture. Intel describes it as moving power routing to the backside so that it is separated from frontside signal routing. Intel’s PowerVia overview describes the approach.
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In a June 2023 account of a product-like test-chip implementation, Intel reported that the structure required thermal mitigation and new design-debug techniques. Those are considerations from Intel’s implementation, not evidence that every backside power design has identical challenges. Intel’s test-chip report provides that context.
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Buried power rails place local power connections near devices, while backside routing supplies power from behind the wafer. Imec’s Naoto Horiguchi, Director of CMOS Device Technology, called combining the two “the most promising implementation scheme” for scalability and performance. That is his attributed assessment of the approach, not a claim that all implementations use this combination. Imec’s report on backside delivery with buried power rails includes the statement.
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