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Samsung Foundry trails TSMC primarily in scale and customer revenue, not because a public test has established one universal yield gap. TrendForce estimated that TSMC captured 70.4% of the top ten foundries’ combined revenue in Q4 2025, versus 7.1% for Samsung Foundry excluding System LSI. Yield is a product- and process-specific result shaped by defects, die size, process control, equipment, learning, utilization and customer demand. Public disclosures do not provide a directly comparable Samsung-versus-TSMC yield percentage.
What “trailing” means in the foundry market
A foundry manufactures chips designed by other companies. Its competitive position is measured through several different lenses: revenue share, available capacity, process technology, yield, delivery, packaging and customer support. Those measures can move in different directions, so “Samsung is behind TSMC” needs a precise definition.
Revenue share shows the scale gap
TrendForce’s March 12, 2026 estimate for the fourth quarter of 2025 put TSMC at 70.4% of the combined revenue of the ten largest foundries. Samsung Foundry, excluding Samsung’s System LSI business, accounted for 7.1%. TrendForce estimated TSMC’s quarterly foundry revenue at $33.7 billion and Samsung Foundry’s at nearly $3.4 billion.
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The comparison is a market-revenue estimate for a defined group of suppliers, not a wafer-yield ranking and not a count of leading-edge wafers. Samsung’s share had risen from 6.8% in the third quarter of 2025, so the latest data describe a very large gap alongside a modest recent improvement rather than an uninterrupted decline.
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| Measure | TSMC | Samsung Foundry | How to interpret it |
|---|---|---|---|
| Q4 2025 share of top-ten foundry revenue | 70.4% | 7.1% (System LSI excluded) | TrendForce market-revenue estimate; not yield data |
| Q3 2025 share of top-ten foundry revenue | 71% | 6.8% | Previous TrendForce quarter and scope |
| Q4 2025 foundry revenue | $33.7 billion | Nearly $3.4 billion | TrendForce estimates, not audited fab results |
Why scale can reinforce itself
A larger customer base and more wafers at a process node generate more production data, more opportunities to identify systematic defects and more leverage to keep expensive equipment busy. High utilization can spread fixed costs over more wafers, while stronger demand can justify faster capacity additions and packaging investment. These effects do not guarantee better yield, but they can make it easier to finance and sustain process learning.
Scale also affects customer confidence. A chip company may value enough capacity for a product launch, predictable delivery, technical support, advanced packaging and a broad ecosystem of design tools. A process node that looks attractive on a specification sheet is not sufficient if a customer cannot secure wafers or meet its shipping schedule.
Why market share is not proof of a yield difference
Yield is the proportion of fabricated dies that satisfy a product’s electrical and functional requirements. It is not a single permanent property of a foundry. The result depends on the exact design, die area, process variant, wafer lot, equipment condition, maturity of the ramp and the definition used for “good” dies.
There is no cited, independently verified, like-for-like public yield statistic for equivalent Samsung and TSMC chips. A percentage without the node, product, die size, test criteria and production stage cannot establish a meaningful head-to-head comparison. Revenue share can reflect demand, pricing, product mix, utilization, capacity and customer launches in addition to manufacturing performance.
What the latest company statements actually say
TSMC’s 2025 Annual Report states: “Our 2-nanometer technology successfully entered high volume manufacturing in 4Q’25, with good yield, and we expect a fast ramp in 2026.” “Good yield” is the company’s qualitative description; it is not a numeric result or an independent benchmark.
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Samsung Electronics’ January 29, 2026 FY2025 results said fourth-quarter Foundry revenue increased with demand from major markets, while provisional costs limited the improvement in earnings. Samsung also described plans to ramp second-generation 2-nanometer products and prepare performance- and power-optimized 4-nanometer processes. Those comments indicate roadmap and cost priorities, but they do not disclose a directly comparable yield rate.
How chip yield is determined
Yield falls when a wafer contains defects or process variation that causes dies to fail electrical or functional tests. Engineers improve it by reducing defect opportunities, tightening process windows, detecting excursions quickly and feeding test results back into production.
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Particles, patterning errors, contamination and equipment-related defects can make a die unusable. Even a low defect density matters when thousands of dies are produced across many wafers. Inspection systems map defects so engineers can distinguish random events from repeating signatures linked to a particular tool, chamber or process step.
Die area and design complexity
A larger die occupies more wafer area and therefore encounters more opportunities for a defect to affect functionality. Samsung’s technical material on 4-nanometer FinFET production explains that increased die area raises defect probability and makes yield harder to maintain, increasing demands on process uniformity and production capability. Complex designs can also contain more sensitive analog, memory, power or high-speed blocks whose specifications narrow the acceptable process range.
Process variation and uniformity
Transistor dimensions, film thickness, line resistance and other parameters vary across a wafer and from wafer to wafer. If variation pushes a parameter outside its electrical window, dies may fail or require lower performance bins. Uniformity across the wafer and across the entire lot is therefore as important as the average measurement.
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Equipment behavior and maintenance
Lithography, deposition, etching, cleaning, metrology and inspection tools must remain within tightly controlled operating conditions. TSMC’s Form 20-F identifies manufacturing-equipment quality as important to semiconductor production. A small drift can affect many wafers before conventional end-of-line testing reveals the problem, which is why tool sensors, preventive maintenance and rapid fault detection matter.
Learning during a process ramp
New nodes generally begin with less production history than mature nodes. Engineers must learn how recipes interact with different designs, reticles, tools and materials. Yield often improves as recurring defects are eliminated, process windows are widened and control limits are refined. A mature 7-nanometer product and a newly launched 2-nanometer product should not be compared using a single “node yield” assumption.
How fabs use data and automation to raise yield
Yield management is an interconnected engineering system rather than one inspection step.
TSMC’s reported methods
In its 2025 Annual Report section on quality and yield advancement, TSMC describes machine learning, neural networks and computer vision for yield analysis, process control, equipment-failure detection, virtual metrology and wafer-defect inspection. Virtual metrology estimates measurements from process and equipment data when a physical measurement is slow or impractical, allowing potential deviations to be flagged earlier.
Samsung’s smart-fab approach
Samsung Foundry describes manufacturing automation and artificial-intelligence technology in its smart-fab operations for yield improvement. Automated material movement, recipe control, equipment monitoring and data analysis can reduce operator variability and shorten the time between an excursion and corrective action. These are company descriptions of methods, not independently measured proof that one supplier achieves a particular yield advantage.
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The feedback loop
- Detect: inspection, metrology, electrical tests and equipment sensors identify an abnormal result.
- Localize: engineers correlate the result with wafer position, lot, tool, chamber, recipe and time.
- Contain: affected wafers or equipment are held while the suspected cause is investigated.
- Correct: the recipe, maintenance state, material flow or process window is adjusted.
- Verify: monitor wafers and subsequent lots confirm whether the change removed the defect without creating another one.
- Learn: the result is added to statistical and machine-learning models used for future detection and control.
Why TSMC’s lead is broader than a yield percentage
TSMC’s advantage is commonly discussed as technology leadership, but customers buy a manufacturing proposition that includes more than transistor density.
Capacity and utilization
Demand determines whether installed capacity is producing wafers. TrendForce linked fourth-quarter 2025 advanced-node demand to tight supply of AI-server GPUs and Google TPUs. In the third quarter, it associated TSMC strength with smartphone and high-performance-computing demand, including flagship smartphone application processors and NVIDIA Blackwell production. A strong product launch can increase a foundry’s revenue even if its process yield has not changed, while weak demand can leave capacity underused.
Product mix and pricing
Foundry revenue combines wafer volume, process pricing and product mix. High-value computing dies, smartphone processors, automotive chips and mature-node components have different prices and volumes. Revenue therefore cannot be converted directly into a yield score.
Ramp costs and profitability
New fabs and nodes incur development, qualification and provisional costs before they reach efficient volume. Samsung specifically cited provisional costs as limiting fourth-quarter earnings improvement in FY2025. Profitability can lag revenue growth during a ramp, even when customer demand is increasing.
Customer service, delivery and packaging
TSMC’s SEC filing discusses customer service, technical support, manufacturing capacity and timely delivery as parts of the foundry proposition. Advanced packaging and the ability to coordinate wafers with packaging capacity are increasingly important for large AI and high-performance-computing systems. A customer may choose a supplier that can deliver a complete, reliable program rather than the supplier with the lowest theoretical defect rate.
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How to compare Samsung Foundry and TSMC without misleading yourself
Use the following framework whenever a headline claims that one foundry is ahead.
- Market measure: identify whether the figure is revenue share, wafer capacity, shipments or another metric; record the quarter and whether Samsung System LSI is excluded.
- Technology stage: specify the exact node, process variant and whether it is development, risk production, qualification or high-volume manufacturing.
- Yield definition: ask whether the number means electrical die yield, functional yield, parametric yield, first-pass yield or another measure.
- Product context: match die size, design complexity, memory and packaging requirements before comparing percentages.
- Commercial context: check utilization, customer demand, pricing, product mix, ramp costs and delivery commitments.
- Evidence quality: separate a company’s qualitative statement from an independently verified measurement.
| Comparison axis | Question to ask | Why it matters |
|---|---|---|
| Scale | Whose revenue or capacity, for which quarter and market scope? | Defines the size of the business but does not measure yield. |
| Node and ramp | Which process and what production stage? | A new node has different learning and cost conditions from a mature one. |
| Yield | Same product, die area, test definition and maturity? | Without matching conditions, percentages are not comparable. |
| Operations | What are utilization, equipment stability and delivery performance? | Manufacturing reliability affects customer outcomes and economics. |
| Customer proposition | Can the supplier provide capacity, support and packaging? | These factors influence sourcing decisions beyond transistor specifications. |
What could change the balance
Samsung’s reported increase from 6.8% to 7.1% of top-ten foundry revenue in Q4 2025 shows that share can move with product shipments and mix. TrendForce said Samsung’s 2-nanometer product shipments and logic-die wafer production for its own HBM4 helped offset slightly lower utilization. Continued improvement would depend on converting roadmap products into stable, high-volume programs, controlling ramp costs and winning enough external demand to keep capacity productive.
TSMC’s stated expectation of a fast 2-nanometer ramp in 2026 gives it a strong starting position, but the outcome still depends on execution, customer schedules, capacity additions and packaging. Neither company’s public statements establish a universal yield number that predicts future market share.
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Samsung Foundry trails TSMC most clearly in the size of its foundry business: the latest cited TrendForce estimate gave TSMC 70.4% and Samsung Foundry 7.1% of top-ten foundry revenue in Q4 2025. That gap should not be recast as a measured yield gap. Chip yield is determined by defect density, die area, variation, equipment control, inspection, automation and accumulated learning, while commercial results also depend on demand, utilization, product mix, cost and customer support. The defensible comparison is therefore node- and product-specific, with every yield claim tied to a definition, date and production stage.
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