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A switched-capacitor filter uses its clock to move charge, so clock-related effects can appear in the output. First identify which effect you have: jitter changes the timing of the filter’s operation and can degrade noise, distortion, or frequency response; clock feedthrough is an unwanted clock-related signal component reaching the output. A cleaner, correctly timed clock addresses timing problems. An output RC filter can attenuate feedthrough only when that component is outside the wanted band. These fixes are not interchangeable.
What “clock noise” means in a switched-capacitor filter
Switched-capacitor (SC) filters are sampled-data circuits. Internal switches and capacitors transfer charge in step with a clock, making clock timing and clock-derived signals part of the filter’s operating environment. The phrase “clock noise” is therefore not a diagnosis by itself. It can refer to different symptoms that call for different fixes.
Jitter is a timing error
Clock jitter means that clock edges do not arrive at exactly the intended times. That perturbs when the circuit samples or transfers charge. The result depends on the pattern of the timing error: Analog Devices’ article Anti-Aliasing Basics Using Switch-Capacitor Filters explains that random phase error raises the noise floor, while periodic jitter can raise total harmonic distortion (THD). Jitter can also degrade stopband response or change measured noise in a particular circuit.
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Clock feedthrough is an unwanted clock-related signal component that reaches the filter output. It may appear as a discrete spur or other clock-related component. If it is outside the signal band, it may already be harmless for the application; a separate output filter is not automatically necessary. If it is in band, a low-pass filter may also remove wanted signal, so simply lowering an RC cutoff is not a reliable answer.
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Do not label every spur “jitter”
A discrete clock-related component, a raised broadband noise floor, and poor stopband attenuation are different observations. A single unexplained spectral line does not establish that jitter is the cause. Linear Technology’s Application Note 40 (AN40), which discusses the LTC1064-1, documents jitter-related changes in response and noise in its own tests; that does not make every clock-frequency spur a jitter symptom.
How to identify the likely cause
Start by comparing the observed problem with the intended signal band and the filter’s clock. Record what changes when the clock source, timing relationship, or output load changes. Use both frequency-domain and time-domain measurements: AN40 recommends evaluating both, because a spectrum alone does not show every settling or timing problem.
- Look at where the unwanted energy sits. Determine whether the observation is a discrete component related to the clock, a broadband noise increase, passband ripple, or unexpectedly weak stopband attenuation. Compare it with the wanted passband and the selected filter’s specified response.
- Check whether the artifact changes with the clock. A clock-related component may move when the clock frequency changes. A noise floor or distortion change as clock quality changes can point toward timing sensitivity, but neither observation alone proves a cause.
- Verify the clock at the filter input. Check stability or jitter, duty cycle, rise and fall times, and logic-level compatibility against the specific device data sheet. A clock generator’s nominal frequency alone does not establish that its waveform meets the filter’s requirements.
- Check the sampling relationship. If an ADC samples the filter output, determine whether the filter and ADC clocks are synchronized and whether conversion occurs after the filter output has had time to settle.
- Assess whether post-filtering is possible. An output RC is a candidate only if there is a frequency range that preserves the wanted signal while attenuating the unwanted component. Include output loading and settling in that decision.
These checks narrow the diagnosis; they are not a substitute for the selected filter’s data sheet or measurements on the actual circuit.
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How to reduce jitter-related problems
Use a clock that meets the particular filter’s requirements
Choose a stable clock with logic levels and waveform timing compatible with the filter. Verify permitted duty cycle and edge characteristics in that device’s data sheet rather than applying one universal limit. Analog Devices’ article Generating Switched-Capacitor-Filter Clocks gives 40% to 60% as general duty-cycle guidance for many manufacturers, while emphasizing that the filter’s own specifications govern. A slow transition through the clock-input threshold can contribute to internal timing uncertainty and unpredictable spurs; the clock edges should cross that threshold swiftly.
AN40 illustrates why the clock deserves attention, but its numerical results belong to one test setup. In an LTC1064-1 test, an approximately 50% jittered clock produced about 42 dB of stopband attenuation at 750 Hz, compared with the cited device specification of 68 dB at 1.5 times cutoff. AN40’s stable-clock trace performed better. This is not a general prediction of how much attenuation any SC filter will lose with jitter.
In a separate AN40 LTC1064-1 comparison, measured noise from 10 Hz to 1 kHz rose from 156 µV RMS to 173 µV RMS with the jittered-clock setup, which the note describes as an approximately 11% increase. Its low-jitter comparison is labeled as less than 1 ns. These figures describe that device and measurement, not a universal noise penalty or jitter threshold.
Synchronize the filter and ADC when their timing relationship matters
If an ADC converts the SC filter’s output, a shared or synchronized clock can make the sampling relationship predictable. Arrange conversion at a repeatable point after the filter output has settled. AN40 recommends synchronizing the A/D and SC filter clocks; Analog Devices also describes a system in which the SC filter and ADC share a clock. The appropriate timing margin depends on the filter, signal, and converter, so use their specifications rather than assuming synchronization alone guarantees settling.
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Related clock generation can also avoid asynchronous beat-frequency artifacts in some arrangements, as described in Analog Devices’ clock-generation article. Whether that is relevant depends on the system’s clock architecture. A related clock is not automatically a low-jitter clock, so verify both the relationship and the waveform at the SC filter pin.
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Understand random versus periodic timing error
Random phase error spreads energy and raises the apparent noise floor. Periodic phase error repeats at a predictable rate and can create discrete modulation products or higher THD. The same nominal peak-to-peak timing number can therefore produce different spectra depending on its distribution. Analog Devices reports a cited example in which 1 ns peak-to-peak jitter reduced SNR in a 16-bit system from 98 dB to 91 dB. That is an example from the article’s referenced investigation, not a conversion rule for every SC filter.
Clock waveform details that are easy to miss
Frequency is only one clock specification. At the filter input, verify the high and low logic levels, duty cycle, rise time, fall time, edge shape, and timing stability. A clock that is nominally at the correct frequency but spends too long near the input threshold can create uncertain internal switching times. Analog Devices states that rising and falling edges should move swiftly through the filter clock input’s threshold.
Use the selected part’s data sheet for the allowable duty-cycle range. The 40%–60% range cited by Analog Devices is general guidance for many manufacturers, not a universal requirement. Some filters specify a narrower range, separate high-time and low-time limits, or minimum edge rates. Confirm the limits at the actual supply voltage and temperature, and inspect the waveform at the IC rather than only at the clock generator.
Also check whether the clock is being loaded by multiple filter inputs or long interconnects. A distorted edge, ringing, or threshold crossing caused by the interconnect can be different from source oscillator jitter. The available documents do not provide a universal PCB layout recipe, so use the component manufacturer’s clock-input and grounding guidance and validate the assembled board.
When an output RC filter can help
An output RC low-pass can reduce feedthrough when the unwanted component is above the wanted passband. Its cutoff must be high enough to preserve the wanted signal and low enough to attenuate the artifact. For a simple first-order RC network, the approximate corner frequency is f = 1/(2πRC); that calculation is only a starting point, not a substitute for checking the complete circuit’s response.
AN40 gives a specific LTC1064-1 example: a 9.64 kΩ resistor and 3300 pF capacitor produce a corner near 5 kHz. In that setup, the measured feedthrough changed from about −61 dB relative to a 500 mV reference (roughly 400 µV) to about −82 dB (roughly 40 µV)—approximately a tenfold reduction. These component values and results are an example, not a recipe for another filter or clock rate.
Check the trade-offs before choosing values
- Wanted-band preservation: Confirm that the RC response does not attenuate signal frequencies or introduce unacceptable response changes.
- Attenuation at the artifact: Estimate or measure attenuation at the actual clock-related component, not just at the nominal cutoff.
- Output loading: Account for the filter’s output impedance and the next stage’s input characteristics; the network must work with the real load.
- Settling: A lower RC corner can lengthen settling. Check the output at the time the next stage samples or uses it.
AN40 notes that a higher ratio of clock frequency to filter cutoff makes feedthrough easier to filter. It also notes that additional post-filtering may be unnecessary when feedthrough is already outside the band of interest. If the unwanted component falls within the wanted band, an output low-pass cannot cleanly separate the two by frequency alone; investigate the circuit and the device guidance instead.
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The 9.64 kΩ/3300 pF network has consequences beyond its calculated pole. The resistor interacts with the SC filter’s output impedance, and the capacitor interacts with the following input, protection structures, and amplifier stability. Check the complete transfer function with the real source and load. A pole that looks acceptable in isolation may move when the next stage is connected. Measure both amplitude response and the time required for the output to settle to the accuracy required by the ADC or other load.
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Clock improvement versus output filtering
| Approach | Best suited to | What to check | Main limitation |
|---|---|---|---|
| Improve clock quality | Jitter-related noise, distortion, or response degradation | Stability or jitter, duty cycle, edge speed, input thresholds, logic levels, and synchronization | Does not necessarily remove a feedthrough component caused by another coupling path |
| Add output RC post-filter | Feedthrough that lies above the wanted passband | Passband loss, attenuation at the artifact frequency, output loading, and settling | May attenuate wanted signal; cannot isolate an artifact that overlaps the wanted band |
Choose based on the diagnosed symptom. An RC filter is not a substitute for a suitable clock, and improving clock timing is not proof that an output feedthrough component will disappear.
Check the surrounding analog implementation
Follow the selected filter’s data-sheet recommendations for supply bypassing and signal coupling. AN40’s general guidance also calls for a linear supply, or a clean switching supply where needed, proper bypassing, attention to aliasing and band-limiting, and checks in both frequency and time domains. These are sound implementation checks, not evidence that a supply problem is present in every design.
Clock lines and sensitive analog nodes should be considered together during measurement. An observed spur can result from electrical coupling into the signal path, from the SC filter’s intended charge-transfer operation, or from timing error. The documents reviewed do not prescribe a universal board-layout pattern, so avoid claiming that one routing change will solve every in-band spur. Instead, compare spectra with the clock enabled, disabled where the circuit permits, or replaced by a cleaner source, and confirm the result at the filter output.
Keep the SC filter’s output feedthrough separate from a different issue: charge injection at a SAR ADC’s switched-capacitor input. Texas Instruments’ reference design discusses an input RC network and filter capacitor to reduce sampling charge injection and band-limit noise, while requiring the amplifier to tolerate the capacitive load and settle adequately. It recommends C0G/NP0 capacitors for that ADC-input application. That network is not automatically the remedy for clock feedthrough generated by an SC filter.
A practical troubleshooting sequence
- Define the symptom: Record the unwanted frequency component, broadband noise, distortion, or response change, and identify whether it lies inside or outside the wanted band.
- Compare against the device specifications: Check the selected filter’s clock limits, passband and stopband behavior, output conditions, and settling guidance.
- Inspect the clock waveform at the device: Verify logic compatibility, duty cycle, edge transitions, and timing stability where the clock reaches the filter.
- Separate jitter from feedthrough: A raised floor suggests a different timing-error signature from a single clock-related line. Change one variable at a time and correlate the result with clock quality or clock frequency.
- Test timing relationships: If an ADC follows the filter, synchronize their clocks where appropriate and verify that conversion occurs after settling.
- Try post-filtering only when frequency separation permits: Select an RC response against the wanted band, artifact frequency, load, and settling requirement, then measure the result.
- Review analog basics: Check bypassing, supply quality, coupling, and aliasing in accordance with the device guidance; do not presume one of these is the cause without evidence.
- Recheck in both domains: Use a spectrum or FFT to quantify spurs, floor, and stopband attenuation, then use a time-domain capture to check clock-to-conversion timing, ringing, and settling.
Measurement and interpretation pitfalls
Do not compare a measured spur in microvolts with a dB figure without stating the reference. AN40’s feedthrough example reports approximately −61 dB and −82 dB relative to a 500 mV reference, corresponding to roughly 400 µV and 40 µV in that setup. A different reference level changes the numerical dB result even when the absolute voltage is unchanged.
Likewise, keep bandwidth attached to a noise number. The 156 µV RMS and 173 µV RMS values were measured from 10 Hz to 1 kHz in the LTC1064-1 comparison. Changing the measurement bandwidth, detector, or loading changes the reported RMS value. The note’s approximately 11% increase should not be generalized to another filter or instrument configuration.
Stopband figures also require frequency context. The cited 42 dB result was measured at 750 Hz with approximately 50% simulated jitter, while 68 dB was the LTC1064-1 specification at 1.5 times cutoff. Those are not interchangeable test conditions. State the filter, clock condition, frequency, and measurement setup whenever quoting a result.
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The AN40 measurements show that clock quality can affect the LTC1064-1’s measured response and noise, and that an RC network reduced feedthrough in one LTC1064-1 setup. They do not establish a universal jitter limit, an expected dB penalty for another filter, or component values suitable for every design. Analog Devices’ jitter discussion explains why random and periodic timing errors can produce different symptoms, while its clock-generation guidance provides general clock-waveform considerations. Use those principles to guide measurement, then apply the limits and recommendations for the exact filter, ADC, and clock implementation.
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Frequently asked questions
Is every clock-frequency spur caused by jitter?
No. A discrete spur may be direct clock feedthrough or coupling, while jitter more often changes the noise floor, distortion, or response. Vary the clock quality and frequency and measure the result before assigning a cause.
Should I always add an RC filter after an SC filter?
No. If feedthrough is outside the application’s band, extra filtering may be unnecessary. Add it only when a pole can preserve the wanted passband while providing useful attenuation at the unwanted component, without unacceptable loading or settling delay.
What duty cycle should the clock have?
Check the selected filter’s data sheet. Analog Devices cites 40% to 60% as general guidance for many manufacturers, but that range is not a universal specification. Also verify rise and fall times and logic thresholds.
Does synchronizing the ADC and filter clocks remove feedthrough?
Synchronization makes the timing relationship predictable and allows conversion after settling; it does not automatically eliminate an output spur caused by clock coupling. Treat synchronization as a timing remedy, not a universal feedthrough cure.
Can a cleaner clock restore stopband attenuation?
It can improve a jitter-sensitive circuit, but the amount depends on the device and test conditions. AN40 measured about 42 dB at 750 Hz with an approximately 50% jittered clock in an LTC1064-1 test versus a cited 68 dB specification at 1.5 times cutoff. Do not apply that difference to another part.
What does the 1 ns jitter example mean for my design?
Analog Devices reports a cited 16-bit example in which 1 ns peak-to-peak jitter reduced SNR from 98 dB to 91 dB. It illustrates sensitivity, not a universal limit. Calculate or measure the timing requirement for the actual filter, signal, and converter.
Are C0G/NP0 capacitors a cure for SC-filter clock noise?
No. Texas Instruments recommends C0G/NP0 capacitors in a particular SAR-ADC input RC application to handle sampling charge injection and noise. That is distinct from clock feedthrough generated by an SC filter. Use capacitor dielectric guidance for the specific network being designed.
What if the feedthrough is inside my wanted band?
A low-pass cannot separate two components that overlap in frequency without also removing wanted signal. Investigate clock routing and coupling, grounding, supply bypassing, synchronization, and the selected device’s application guidance, then verify changes with measurements.
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Bottom line
Start with classification. Random clock timing error can raise the noise floor, periodic jitter can raise distortion, and clock feedthrough can appear as an unwanted output component. Improve the clock when timing quality or waveform compliance is the problem; synchronize clocks when conversion timing and settling matter; use an output RC only when the artifact is out of band and the required attenuation is compatible with passband, loading, and settling. Keep every numeric expectation tied to the exact filter and test setup, and confirm the fix in both frequency and time domains.
Frequently Asked Questions
Is every clock-frequency spur caused by jitter?
No. It may be direct clock feedthrough or coupling. Jitter more commonly changes noise floor, distortion, or response, so vary clock quality and frequency and measure before assigning a cause.
Should every switched-capacitor filter have an output RC filter?
No. If feedthrough is outside the application band, extra filtering may be unnecessary. Use an RC only when it preserves the wanted signal and settling while attenuating the artifact.
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What clock duty cycle is acceptable?
Use the selected filter’s data sheet. The 40%–60% range is general guidance cited for many manufacturers, not a universal limit; edge speed and logic thresholds also matter.
Does clock synchronization remove feedthrough?
No. It makes timing predictable and supports settling before conversion, but it does not necessarily eliminate a spur caused by clock coupling.
Can a cleaner clock restore stopband attenuation?
It may improve a jitter-sensitive circuit, but the result is device- and setup-dependent. The LTC1064-1 figures in AN40 are not universal.
What does the 1 ns jitter example prove?
It illustrates that timing error can reduce SNR; Analog Devices’ cited 16-bit example fell from 98 dB to 91 dB. It is not a universal jitter limit.
Are C0G/NP0 capacitors a cure for SC-filter clock noise?
No. The cited C0G/NP0 recommendation applies to a particular SAR-ADC input RC network, not automatically to an SC filter’s clock feedthrough.
What should I do when feedthrough overlaps the wanted band?
A low-pass cannot separate overlapping frequencies cleanly. Investigate coupling, routing, grounding, bypassing, synchronization, and device-specific guidance, then measure the result.
The Bottom Line
Classify the symptom before changing the circuit: jitter affects timing, while feedthrough is a clock-related output component. Use a compliant, stable clock and synchronize it with the ADC when timing matters. Add an output RC only when the unwanted component is out of band and the pole does not compromise passband or settling. Validate the exact implementation in both frequency and time domains.
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