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Before moving a chip to another foundry process, prove that the target technology can meet the product’s electrical requirements, that its PDK and EDA flow are mature enough for signoff, that every hard IP block can be replaced or requalified, and that qualification, packaging, yield and supply plans are credible. A similar node name or a clean tapeout on the source process is not evidence that the design will transfer unchanged.
Start with a written process-fit specification
Capture the product requirements before comparing foundries. The target process must be evaluated against the actual operating envelope, not a marketing label such as “180 nm” or “7 nm.” Create a requirements sheet that includes:
- Voltage domains, I/O voltages, maximum and minimum operating conditions, and level-shifting needs.
- Clock targets, throughput, latency, standby and active-power limits, and leakage budget.
- Analog, RF, high-voltage, isolation, noise, matching and linearity requirements.
- Memory types and sizes, including SRAM, ROM, eFuse or embedded nonvolatile memory.
- I/O standards, SerDes or PHY requirements, ESD targets and package connections.
- Metal-stack, current-density, electromigration, thermal and interconnect-length requirements.
- Automotive, industrial, medical, aerospace or consumer reliability class and expected product life.
Compare each item with a specific option in the target process. A process portfolio can differ substantially in high-voltage devices, low-leakage variants, embedded memory, RF components and mixed-signal support. Two processes with similar nominal geometries may therefore require entirely different circuit architectures.
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Define non-negotiable constraints
Mark requirements that cannot be traded away, such as an interface voltage, a memory compiler, a temperature range or a safety qualification. Then identify desirable targets, such as a power reduction or smaller die. This distinction helps determine whether a process mismatch is a project-ending issue or a redesign opportunity.
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Obtain and control the target PDK
Request the current target-process PDK through the foundry’s controlled access process, including release notes and change history. The PDK is the contract between the process and your design tools: it supplies device models, layer definitions, design rules, extraction data, reliability guidance, standard-cell libraries, memory views and signoff decks.
Check PDK contents and maturity
Confirm that the release contains, at minimum:
- SPICE and statistical models for every device and voltage option you will use.
- Standard-cell, I/O, memory and specialty-library timing, power and physical views.
- Layer-purpose definitions, technology files, parasitic extraction rules and antenna data.
- DRC, LVS, electrical-rule, ESD, latch-up, density and reliability decks.
- Supported synthesis, simulation, place-and-route, extraction and signoff tool versions.
- Known-issue lists, errata, migration notes and a documented waiver process.
Ask whether the release is production-qualified, engineering-only or still changing. Freeze the exact PDK version in configuration management and record which design databases, scripts and signoff runs depend on it. A late rule or model change can invalidate previous timing, extraction or physical-verification results.
Build a rule and layout delta list
Do not begin with an assumption that the source layout can simply be scaled. Compare source and target rules line by line, then classify each difference as an automatic translation, a manual redesign or a potential blocker.
Physical differences to identify
- Layer count, layer purposes, minimum widths and spacings, preferred directions and coloring requirements.
- Via types, via arrays, enclosure rules, cut spacing and allowed metal combinations.
- Density, metal fill, slotting, dummy structures and pattern-dependent restrictions.
- Antenna limits, well and implant rules, latch-up structures, guard rings and deep-well options.
- ESD devices and routing, current-density limits, electromigration rules and thermal constraints.
- Special analog matching, resistor, capacitor, inductor and RF layout requirements.
Separate mandatory rules from design guidance. The GF180MCU documentation, for example, distinguishes process-specific mandatory DRC checks from recommendations and requires a waiver before tapeout acceptance when a mandatory test is violated. Its exact limits apply to that PDK; they should not be generalized to another process.
Plan for translation limits
A layout-versus-schematic-clean source database can still fail target DRC or produce different parasitics. Retain the source layout as a reference, but expect to redraw device structures, wells, guard rings, matching patterns, critical routes and power grids where the target rules require it.
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Inventory every IP block and macro
Create an IP register before selecting a foundry. Include SRAM and ROM compilers, PLLs, SerDes, PHYs, I/O cells, ADCs and DACs, sensors, RF blocks, security elements, embedded memories and third-party hardened macros. For each item, record the following evidence:
| Question | Evidence to obtain |
|---|---|
| Does an exact target-process version exist? | Foundry or IP-provider catalog entry, supported process variant, voltage and temperature range. |
| What does it deliver? | Timing, power, area, noise, jitter, linearity, bandwidth and other applicable specifications. |
| Has it been characterized? | Corner data, silicon or test-chip results, reliability characterization and revision history. |
| What are the usage conditions? | Required libraries, metal stack, package assumptions, clocking, supply limits and integration constraints. |
| Who supports it? | License terms, modification rights, maintenance contact, response commitments and end-of-life policy. |
TSMC describes process-specific IP lifecycle assessments that can include pre-silicon review and test-chip assessment. It also expressly warns that silicon-verified IP is not guaranteed to work in every design environment or achieve a particular production yield. Treat verification status as evidence, not a promise.
TSMC reported a catalog of more than 60,000 IPs in August 2023, spanning dozens of IP types and hundreds of its process technologies. That is a historical ecosystem figure, not a current availability count and not proof that a particular macro exists for your target node.
Decide what happens to unavailable IP
For every missing macro, choose one path: obtain a target-qualified replacement, redesign the block, license a soft implementation, or remove the feature. Include the schedule and verification impact of that choice. A single unavailable memory compiler or high-speed PHY can dominate the port even when the rest of the digital logic is straightforward.
Verify EDA tools and the migration flow
Ask the foundry for certified tool names and versions, not merely a list of compatible vendors. Confirm a reference flow for synthesis, static timing, simulation, physical implementation, parasitic extraction, physical verification, reliability analysis and final data preparation.
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Check digital-flow coverage
- Run synthesis with the target standard-cell and memory libraries.
- Use target timing, power and physical abstracts during floorplanning and place-and-route.
- Extract parasitics with the target technology files and signoff corners.
- Run static timing, power integrity and electrical checks at all required operating corners.
- Execute the foundry-certified DRC, LVS, antenna, density and reliability decks.
Confirm that automation scripts, layer maps, constraints, extraction settings and waiver files are supported by the target release. A flow that works on a demonstration block may still lack a required signoff check for your product class.
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Analog and RF migration is rarely a database conversion. It may involve schematic translation, device resizing, bias redesign, layout reuse, new matching structures, re-extraction, simulation and circuit optimization. TSMC’s EDA material describes reference flows for particular analog and RF technology transitions; that support is specific to the named transition and should not be treated as universal portability.
Re-establish PPA and circuit behavior
Re-run the complete design with target-process models, libraries, parasitics and operating corners. Compare more than headline frequency and area:
- Setup and hold timing, clock uncertainty, useful skew and interface margins.
- Dynamic, leakage, inrush and retention power across realistic workloads.
- Die area, routing congestion, memory placement and power-grid requirements.
- Analog offset, gain, noise, matching, linearity, phase noise and settling time.
- Voltage and temperature margins, aging, mismatch and process variation.
Separate measured results from estimates and preserve the conditions for every comparison. Process gains are process- and design-specific. TSMC states that its N6 process retains backward-compatible design rules, models, IP and the same design flow and EDA availability as N7. That is an engineered compatibility case within one platform, not a general rule for moving between unrelated foundries.
Budget redesign, not just retargeting
Use early synthesis, memory selection and a small physical test block to expose changes in cell density, wire delay, leakage and congestion. For analog, include corner and Monte Carlo work where mismatch or yield matters. Do not promise a PPA improvement until the target models and extracted layout support it.
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Repeat verification and define tapeout acceptance
Source-process signoff does not demonstrate target-process compliance. Establish a target signoff matrix that identifies the deck, owner, run status, waiver authority and acceptance criterion for every check.
Required signoff questions
- Which DRC, LVS, extraction, antenna, density, ESD, latch-up and electrical checks are mandatory?
- Which reliability analyses are required for the intended voltage, temperature and lifetime?
- What data formats, layer maps, mask options and seal-ring structures does tapeout require?
- How are violations documented, reviewed and waived, and which waivers are unacceptable?
- Which final database, report and checksum package will the foundry accept?
GlobalFoundries states in its foundry-service specification that designs must pass all DRC tests before data submission. Obtain the current target documentation and acceptance checklist directly; requirements can vary by process and release.
Assess qualification, reliability and manufacturing readiness
A technically clean design can still fail as a product if the process, package or supply chain is not ready. Request evidence relevant to your market and lifetime:
- Process qualification status, release criteria and applicable reliability reports.
- Operating-life, electromigration, time-dependent dielectric breakdown and temperature-cycle data.
- Characterization plans for new devices, memories, analog blocks and I/O options.
- Failure-analysis methods, laboratory support and corrective-action procedures.
- Package, assembly and test compatibility, including thermal and electrical limits.
- Wafer acceptance criteria, defect-density monitoring and yield-learning visibility.
- Manufacturing sites, capacity reservations, lead times and lifecycle commitments.
TSMC describes technology qualification before transfer to fabs and quality and reliability controls from development through mass production. Those general practices do not establish the qualification status, expected yield, lead time or capacity for a particular process or customer product. Request product-specific evidence under the appropriate confidentiality agreement.
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Estimate schedule, cost and ownership from the real scope
There is no defensible universal port price or duration. Build the estimate from the work your design actually requires:
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| Work package | Cost and schedule drivers |
|---|---|
| PDK onboarding | Access approval, tool installation, version qualification, training and flow debugging. |
| IP replacement | New licenses, macro integration, characterization, redesign and support agreements. |
| Implementation and verification | Floorplan changes, analog redesign, extraction, signoff closure and waiver review. |
| Risk reduction | MPW or test-chip runs, additional masks, silicon bring-up and failure analysis. |
| Product qualification | Package and test development, reliability testing, regulatory or market-specific approval. |
| Ramp | Tapeout slots, wafer starts, assembly capacity, yield learning and inventory policy. |
Assign an owner for every migration task and clarify who may modify, re-characterize or reuse third-party IP. Obtain commercial quotes, tapeout-slot commitments and supply terms directly from the foundry and suppliers. Keep engineering estimates separate from contractual commitments.
Compare candidate processes with one evidence-based scorecard
Use the same questions for every candidate rather than scoring public marketing claims. Require a document, demonstration or named contact for each answer.
| Evaluation area | What to compare |
|---|---|
| Electrical and process fit | Voltage, performance, power, analog/RF, memory, I/O and reliability requirements. |
| PDK maturity | Release status, model coverage, rule stability, extraction quality and signoff-deck completeness. |
| IP and macros | Target versions, characterization, licensing, support and replacement effort. |
| EDA enablement | Certified versions, reference flows, scripts, migration aids and support response. |
| PPA and redesign burden | Expected timing, power, area, noise, matching and manual redesign work. |
| Verification and reliability | Required checks, qualification data, failure analysis and waiver policy. |
| Package and test | Assembly options, thermal limits, test access and production compatibility. |
| Business and supply | Schedule, total cost, capacity, lifecycle, ownership and contractual terms. |
Do not award a high score because a process has a familiar node name or a large ecosystem statistic. A candidate is viable only when its evidence covers your specific design, product conditions and production plan.
A practical go/no-go review
Hold the decision review after a target-flow pilot, not after a marketing presentation. Require these outputs:
- A signed process-fit matrix with unresolved gaps and mitigation owners.
- A frozen PDK and tool-version manifest with known issues recorded.
- An IP disposition list showing qualified, replace, redesign or remove for every macro.
- Early PPA results from target libraries, models and extracted test structures.
- A target signoff matrix and tapeout data checklist.
- A qualification, package, test, yield and supply evidence pack.
- A bottom-up schedule and cost estimate with contingency for silicon learning.
Stop or redesign the plan if a non-negotiable requirement lacks a target-process device or IP, if signoff coverage is incomplete, or if qualification and supply evidence cannot support the intended product launch. Proceed when the remaining gaps are explicit, funded and owned rather than hidden behind assumed portability.
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