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Before choosing a silicon-carbide (SiC) or gallium-nitride (GaN) switch, define the converter’s voltage, power, topology, frequency, isolation, cooling and regulatory envelope. Then select the transistor, gate driver, bias supply, protection, layout and EMI controls as one system. Wide-bandgap devices can make a supply smaller and faster, but their steep voltage and current edges expose parasitic inductance, ringing, common-mode noise and thermal limits that a slower silicon design may hide.
1. Freeze the operating envelope before selecting a device
A material label is not a design specification. Record the conditions the switch must survive and the performance the complete supply must deliver. These values determine whether SiC, GaN or neither is appropriate.
| Parameter | What to record | Why it changes the design |
|---|---|---|
| Input and output | Minimum, nominal and maximum bus voltage; output range; transients and ripple | Sets voltage stress, modulation range, insulation requirements and control headroom. |
| Power and current | Continuous, peak and overload current; duty cycle; load-step profile | Determines conduction loss, thermal mass, current sensing and fault energy. |
| Topology | Half-bridge, full-bridge, LLC, flyback, boost, inverter or another architecture | Changes commutation paths, body-diode or reverse-conduction behavior, deadtime and driver requirements. |
| Switching target | Nominal frequency, allowable frequency range and transition-time goal | Trades magnetic and filter size against switching loss, EMI and measurement difficulty. |
| Isolation | Functional, basic or reinforced isolation; working voltage; pollution and altitude assumptions | Determines creepage, clearance, insulation system, isolated drivers and bias supplies. |
| Environment | Ambient temperature, cooling method, enclosure, humidity, vibration and expected lifetime | Sets junction-temperature margin, package choice and reliability analysis. |
| Fault envelope | Short circuit, overload, inrush, shoot-through and brownout conditions | Sets protection speed, blanking time, energy limits and restart behavior. |
| Market and compliance | Target countries, emissions limits, safety category and product-level standards | Determines the insulation, EMI filter, test and documentation work that must be designed in. |
The intended voltage, topology, isolation class and geography are often unknown at the concept stage. Do not choose a particular part number, protection threshold or compliance standard until those decisions are explicit.
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2. Compare SiC and GaN against system limits
Compare actual devices in the same voltage class, current range, package style and topology. Neither technology is a universal winner.
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| Comparison axis | Questions to answer |
|---|---|
| Electrical margin | What are the rated voltage and current, and what overshoot and transient margin remain at the real bus? |
| Losses | What are conduction and switching losses at the actual temperature, load, bus voltage and frequency, rather than at a headline test point? |
| Gate interface | What gate-voltage range, total gate charge, peak source/sink current and allowable negative gate voltage does the datasheet specify? |
| Speed versus tolerance | Can the PCB, package and isolation system control the edge rate without excessive ringing, common-mode current or insulation stress? |
| Thermal path | How do package thermal impedance, copper area, heatsink and cooling method work together over the full duty cycle? |
| Protection | Does the driver provide suitable overcurrent or desaturation response, undervoltage lockout (UVLO), soft shutdown and fault reporting? |
| Implementation ecosystem | Are compatible drivers, isolated bias supplies, sensors, layout references and replacement parts available for the product lifetime? |
Infineon’s high-reliability comparison uses a GaN example with a rise time below 5 ns and a gate-source range of −5 V to +6 V. Those numbers describe that example, not every GaN transistor; use the selected device’s current datasheet for limits.
3. Choose switching frequency and edge speed as a trade-off
Higher frequency can shrink transformers, inductors and filters, but it increases switching events per second and usually makes every parasitic more consequential. A faster transition can reduce switching energy at one operating point while increasing overshoot, ringing, common-mode current, EMI and insulation stress elsewhere.
Set a loss budget
Estimate turn-on, turn-off, conduction, reverse-conduction, driver and magnetic losses at minimum and maximum input voltage and load. Include deadtime and light-load modes. Do not assume the fastest available gate setting gives the highest system efficiency; a modestly slower edge may reduce snubber, filter and cooling requirements enough to improve total performance.
Relate gate charge to the frequency target
Gate-driver average supply current is approximately proportional to gate charge multiplied by switching frequency. Peak driver current controls transition time, while gate resistance and loop inductance shape the actual waveform. Select source and sink capability from the datasheet charge curves and the required transition, then verify it on the assembled board.
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Account for magnetic and insulation effects
At higher frequency, magnetic cores may run hotter even when they are smaller, and winding capacitance can transfer fast common-mode currents. Fast switch-node movement also increases electric-field stress across isolation barriers. Treat magnetics, insulation and the EMI filter as part of the frequency decision rather than as cleanup work.
4. Design the gate driver and bias supply around the selected switch
The driver is part of the power stage. Read the switch and driver datasheets together and check every limit under the expected negative switch-node excursion.
- Gate voltage: stay within the specified turn-on, turn-off and absolute maximum ranges. A narrow allowable range leaves little room for ringing.
- Gate charge and current: size source and sink current for the desired rise and fall times, including separate turn-on and turn-off resistors when needed.
- Timing: verify propagation delay, channel matching, minimum pulse width and deadtime over temperature and supply voltage.
- CMTI: choose a common-mode transient immunity rating that exceeds the measured switch-node slew, with margin for production variation.
- UVLO and startup: confirm the driver does not partially enhance the device during bias ramp, brownout or a controller reset.
- Negative transients: check the driver input and output ratings when the source or switch node moves below ground.
- Fault response: define how an overcurrent, desaturation, short circuit or driver fault turns the switch off and how the controller latches or retries.
Provide a clean bias supply
The gate-bias supply affects efficiency, reliability and EMI. Determine whether each high-side or low-side channel needs an isolated output, what peak and average gate power it requires, and how much capacitance can be placed at the driver pins. Transformer capacitance in an isolated bias converter can couple switch-node common-mode noise into control or chassis domains.
Texas Instruments discusses LLC and flyback approaches for isolated gate-driver bias supplies. The suitable topology depends on output count, required isolation, bias power, transient behavior, EMI and reliability—not on a universal preference for one converter type.
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5. Lay out the gate and commutation loops as high-frequency circuits
At nanosecond edge rates, a few millimeters of copper can add enough inductance to create damaging voltage. Texas Instruments’ layout guidance states, “A good layout helps reduce the amount of parasitic inductances or capacitances in the design.” Apply that principle to the complete current path.
Gate loop
- Place the driver, gate resistor and switch gate source/emitter connection close together.
- Route a dedicated gate return; do not share it with a noisy power return.
- Keep the loop area small and avoid vias unless their inductance is included in the design.
- Place high-frequency driver decoupling directly across the driver supply pins.
Commutation loop
- Minimize the loop formed by the high-side switch, low-side switch, DC-link capacitors and return path.
- Use a low-inductance ceramic or film capacitor at the bridge; a distant bulk capacitor cannot control the fastest current edge.
- Control switch-node copper area and keep it away from gate, feedback, clock and isolation traces.
- Give sensitive signals a deliberate reference plane and avoid routing them beneath the switch node.
TI guidance for the GaN designs it addresses calls for at least four PCB layers. That is a recommendation for those designs, not a universal rule for every SiC or GaN supply. Layer count must follow the required current return, controlled impedance, thermal spreading and isolation geometry.
6. Coordinate protection with the device’s real fault behavior
Protection must remove energy before the selected switch exceeds its short-circuit, pulse-current or junction-temperature limit. Set blanking times, thresholds and soft-shutdown behavior from the device datasheet and the measured driver delay, not from a generic value.
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One Texas Instruments comparison gives approximate short-circuit withstand figures of 2 microseconds for SiC and 10 microseconds for IGBTs. These are broad contextual examples, not guaranteed limits for any particular transistor; actual withstand varies with part, bus voltage, temperature, gate drive and fault type.
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- Detect shoot-through and enforce hardware deadtime.
- Limit inrush and handle output short circuits without repeated destructive restarts.
- Define overvoltage, undervoltage, overtemperature and loss-of-feedback responses.
- Check whether protection remains active during controller startup, auxiliary-bias loss and isolation faults.
7. Build the thermal path before calculating efficiency
Calculate junction temperature from conduction and switching losses at the worst electrical and ambient conditions. Include driver dissipation, magnetic loss, snubber loss and PCB copper temperature. Package thermal impedance depends on board copper, vias, airflow and heatsinking, so a datasheet value measured on a reference board is not automatically your product’s result.
Verify temperature rise at nominal load, peak load, minimum and maximum bus voltage, and the intended switching frequency. Thermal cycling, not just steady-state temperature, can limit solder joints, bond wires, capacitors and isolation materials.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.8. Plan isolation and EMI before the first prototype
Fast common-mode currents flow through device capacitances, transformer interwinding capacitance, heatsinks and measurement equipment. Map those paths during schematic review. Keep creepage and clearance consistent with the required insulation class, working voltage, pollution degree and altitude for the target market.
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9. Validate the assembled layout, not an ideal schematic
- Check static limits: confirm voltage, current, gate, driver, isolation and thermal margins against current datasheets.
- Probe safely: use probes and bandwidth appropriate for the edge rate, with the shortest practical ground connection. Poor probing can create ringing that is not present—or hide ringing that is.
- Capture switching waveforms: measure gate voltage, switch-node voltage, drain-source overshoot, ringing frequency, deadtime and Miller behavior at several loads and bus voltages.
- Measure fault response: verify overcurrent or desaturation timing, shutdown polarity, latch/retry behavior and energy during a controlled fault test.
- Measure temperatures: record switch, driver, magnetics, capacitors and heatsink temperatures after thermal equilibrium and during transients.
- Run EMI and isolation tests: check conducted and radiated emissions, common-mode current and dielectric withstand or insulation-monitoring behavior required by the product.
- Repeat across corners: include component tolerances, temperature extremes, minimum and maximum input, light and full load, startup and shutdown.
Published reference-design results apply only to the documented board, firmware, components and test conditions. They are useful benchmarks, not guarantees for a new layout.
10. Use reference designs as bounded examples
TI TIDA-00909
This Texas Instruments reference design is a 48 V, 10 A three-phase GaN inverter for high-speed drives. It uses an 80 V GaN half-bridge power stage, provides design files and reports up to 98.5% peak efficiency at 100 kHz PWM under its stated test conditions. It is not a general-purpose power-supply board; its value is showing one implementation of low-voltage GaN commutation, layout and control.
TI PMP30934
PMP30934 is an automotive IGBT/SiC gate-drive auxiliary power supply with isolated outputs. It is relevant when studying bias-supply architecture, but its automotive application, output arrangement and qualification assumptions must be checked before applying any circuit to another product.
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Keep one controlled record containing the operating envelope, selected-device datasheet revision, loss budget, gate-drive calculations, isolation assumptions, protection timing, PCB loop sketches, thermal model, EMI plan and validation results. Require every change to switching frequency, gate resistance, package, DC-link capacitor, heatsink or isolation component to trigger a review of the dependent calculations and tests. This change control is especially important with SiC and GaN because a small parasitic or timing change can alter overshoot, EMI and fault energy together.
Bottom line
Choose SiC or GaN only after the application envelope is fixed. The reliable design process is system-level: select the switch from voltage, current, loss and thermal limits; set frequency and edge speed with EMI and insulation costs visible; match the driver and bias supply to the exact gate behavior; minimize gate and commutation parasitics; implement device-specific protection; and validate the final board across electrical, thermal, fault and compliance corners. Without those inputs, naming a “best” device or frequency would be guesswork.
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