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RDMA, SmartNICs and DPUs, and computational storage improve different parts of an AI system’s data path. RDMA changes how data is transferred so a capable adapter can place data directly in memory with less host-CPU copying. SmartNICs and DPUs offload networking, security, and storage services from the server CPU. Computational-storage devices perform selected filtering, transformation, or inference operations near the storage media before all data travels to a host or accelerator.
They are complementary architectural options, not interchangeable products or a package every AI server needs. The right choice depends on whether the bottleneck is network movement, host infrastructure work, or unnecessary data movement from storage.
Start with the AI data path
A training or inference job repeatedly moves data through several stages. Datasets live on local drives or shared storage. Storage software reads files or objects, the host operating system and CPU prepare them, a network may move them between machines, and CPUs or accelerators consume the result. Every handoff can add latency, memory copies, CPU work, or network traffic.
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These technologies intervene at different points:
- RDMA is a data-movement capability. It lets a capable device transfer data to or from memory without routing every byte through the host CPU’s ordinary copy path.
- SmartNICs and DPUs are infrastructure devices. They accelerate or run networking, security, storage, and management functions that would otherwise consume host-CPU cycles.
- Computational storage places selected computation close to the storage device, so unwanted or untransformed data does not have to travel as far.
Reducing one form of overhead does not automatically improve an end-to-end job. Protocol setup, drivers, topology, software integration, queueing, and the workload itself determine whether a bypass or offload produces a measurable benefit.
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What RDMA does for AI systems
Direct memory transfers with fewer host copies
Remote direct memory access allows a network-capable device to read from or write to memory on another system, subject to permissions and software setup. The transfer can avoid the conventional sequence in which the host CPU copies data between application buffers, kernel buffers, and the network adapter. Less CPU participation can leave more processing capacity for data preparation and orchestration, while reducing intermediate memory traffic.
In distributed training, RDMA can carry parameter exchanges, gradients, and other synchronization traffic between servers. In inference or data serving, it can move batches or feature data between machines with predictable latency when the fabric and software are correctly configured. RDMA is not itself a guarantee of lower latency or higher throughput; a poorly matched workload, congested fabric, or inefficient application can erase the potential gain.
RDMA versus GPUDirect RDMA
RDMA is the general capability. NVIDIA’s GPUDirect RDMA is a vendor implementation and ecosystem that enables direct communication between NVIDIA GPUs in remote systems through supported network adapters and software. NVIDIA’s broader GPUDirect family also includes GPUDirect Storage, which can let supported storage devices read or write GPU memory directly.
Those names should not be treated as synonyms. A deployment can use ordinary RDMA between host memories, while GPU-to-GPU transfers require compatible GPUs, adapters, drivers, libraries, firmware, and topology. A direct path still depends on memory registration, protection, queue management, and application support.
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Fabrics and examples
RDMA can run over specialized fabrics and over Ethernet using protocols such as RoCE v2. AMD’s Embedded RDMA Enabled NIC documentation, version 4.2 released December 19, 2024, lists sensor-data transfer, video and image transfer, and remote storage nodes over RoCE v2 as example applications. These examples show that RDMA is useful for data movement beyond one GPU vendor’s stack; they do not establish that every listed deployment is AI-specific.
What SmartNICs and DPUs do
From a conventional NIC to an infrastructure accelerator
A conventional network interface controller connects a server to a network and handles packet transmission, reception, and basic processing. A SmartNIC adds hardware acceleration, programmability, or both. It can perform functions such as virtual switching, packet classification, telemetry, encryption, storage protocols, and traffic isolation while reducing work on the host CPU.
A DPU is a programmable processor class designed to offload, accelerate, or isolate data-centric infrastructure tasks. Depending on the product, that can include networking, security policy, storage services, virtualization, and management-plane functions. “SmartNIC,” “DPU,” and “SuperNIC” are not universal synonyms: vendors use the labels differently, so evaluate the actual engines, cores, memory, interfaces, and supported software.
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Why an AI server might use one
AI servers often contain expensive CPUs whose primary job is to feed accelerators and coordinate jobs. A DPU or SmartNIC can terminate network services, enforce tenant isolation, process storage traffic, or run security functions on its own resources. This can make the host CPU’s workload more predictable and can create a clearer security boundary between infrastructure services and user workloads.
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NVIDIA’s BlueField DPU and ConnectX SmartNIC families are vendor examples, and NVIDIA’s DOCA software supplies libraries, services, and management tools for those platforms. Its DOCA overview advertises connectivity of up to 800 gigabits per second (Gb/s) for the described platform. That is a vendor capability statement, not a universal SmartNIC speed and not a workload benchmark. Actual throughput depends on the specific adapter, port configuration, protocol, PCIe generation, and software path.
What a SmartNIC or DPU does not do
Offloading infrastructure does not make an application automatically faster. The host still has to submit work, manage buffers, and handle functions that the device does not support. Programmable devices also add firmware, SDK, lifecycle, and observability requirements. A team that cannot operate the device’s software stack may gain little from theoretical acceleration.
What computational storage does
Compute near the data
Computational storage places processing resources in or near a storage device. Instead of reading every byte into host memory and then transforming it, the device can execute selected operations such as filtering records, converting formats, extracting features, or running a constrained inference step. Only the result, or a smaller subset of the original data, then moves to the host or accelerator.
The useful unit is the operation, not the marketing label. “Computational storage” does not mean an entire large language model or training job runs inside an SSD. It means that a supported device performs defined work close to where data resides. The operation may be worthwhile when datasets are large, filtering is selective, and the host or network would otherwise move substantial amounts of data that will be discarded.
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Standards and interoperability
The Storage Networking Industry Association (SNIA) publishes a Computational Storage Architecture and Programming Model. The current page lists version 1.2, published April 21, 2026, and defines recommended behavior for hardware and software that supports computational storage. SNIA’s Computational Storage Technical Work Group, marked updated April 2025, focuses on interoperability and interface standards.
A standard describes models and interfaces; it does not mean every drive supports the same operations. Devices can differ in compute resources, supported functions, programming methods, security controls, data formats, and host APIs. Confirm the exact operation and software support for a chosen device before designing an application around it.
How the three technologies can work together
A possible AI pipeline uses each technology for a different job. This is an architectural pattern, not a requirement that all three appear in one system.
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errors- Storage reads the source data. A computational-storage device filters corrupt records, selects a date range, converts a format, or performs another supported near-storage operation.
- The reduced or transformed result moves toward the compute node. If the storage path and software support a direct mechanism such as GPUDirect Storage, data may be placed in GPU memory without the traditional host-copy sequence.
- The network connects machines or accelerators. RDMA can transfer buffers between systems with less host-CPU involvement. For GPU-aware paths, GPUDirect RDMA requires compatible GPUs, adapters, drivers, and topology.
- Infrastructure services run off the host. A SmartNIC or DPU can handle virtual networking, encryption, storage protocols, telemetry, and isolation while the host CPU coordinates the application.
- The accelerator runs the model. GPUs or other accelerators consume the prepared data. The best design is the one that removes the actual bottleneck rather than adding every available device.
Comparison by architectural role
| Technology | Where it acts | Work it reduces or moves | Key dependencies | What it is not |
|---|---|---|---|---|
| RDMA | Network and memory-transfer path | Host copies and CPU involvement in remote-memory transfers | RDMA-capable adapters, fabric, drivers, memory registration, application support | Not a storage processor or a guarantee of faster end-to-end jobs |
| SmartNIC | Server network interface | Packet processing, virtual switching, telemetry, and selected security or storage functions | Hardware accelerators, firmware, vendor SDK, host integration | Not automatically a DPU, and not a replacement for the host CPU |
| DPU | Dedicated programmable infrastructure processor | Networking, security, storage, virtualization, and management services | Device cores and memory, isolation model, software stack, operational tooling | Not a universal synonym for every SmartNIC or SuperNIC |
| Computational storage | Inside or next to storage | Selected filtering, transformation, feature extraction, or inference before wider data movement | Device compute capability, supported APIs, data formats, security and orchestration | Not an entire AI model running inside an SSD |
Choosing the right intervention
Choose RDMA when network movement dominates
Measure whether distributed workers spend significant time exchanging gradients, parameters, batches, or remote-memory buffers, and whether host CPU utilization or memory copies are visible in traces. RDMA is most relevant when both endpoints, the fabric, and the application can use it efficiently. If the bottleneck is model computation, disk latency, data decoding, or a congested switch, RDMA alone will not solve it.
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Choose a SmartNIC or DPU when infrastructure work consumes the host
Look for CPU time spent on virtual switching, packet processing, encryption, storage services, or tenant-isolation controls rather than on the model or data pipeline itself. A DPU can also help when infrastructure must be isolated from customer or training workloads. Compare the device’s supported offloads and software maturity, not just its product category.
Choose computational storage when most moved data is unnecessary
Profile selectivity: how much data can be rejected, transformed, or summarized before it leaves storage? Near-storage processing is attractive when the answer is substantial and the operation maps cleanly to the device API. It is less compelling when nearly every byte is needed by the accelerator, the operation is too complex for the device, or data must be decoded on the host anyway.
Deployment requirements and failure modes
- Compatibility gaps: GPU-aware direct paths require matching GPU, adapter, firmware, driver, runtime, and topology versions. Verify the complete support matrix rather than assuming that two devices with “RDMA” labels interoperate.
- Fabric configuration: RoCE deployments can require careful loss-management, quality-of-service, congestion, and switch configuration. A misconfigured fabric can produce retransmissions and unpredictable latency.
- Copy-path assumptions: Bypassing the CPU does not remove setup, synchronization, memory-registration, or application overhead. Benchmark the complete pipeline, including preprocessing and queueing.
- Software lifecycle: SmartNICs and DPUs add firmware, SDK, driver, and monitoring updates. Computational-storage devices add device programs and API compatibility concerns.
- Security boundaries: Offloaded services still need authentication, authorization, isolation, secure boot, and update controls. Moving code away from the host does not make it automatically trusted.
- Operational visibility: Instrument host CPU time, memory copies, network utilization, queue depth, storage latency, accelerator occupancy, and dropped or retried operations before and after a change.
What the available performance claims mean
Vendor pages describe intended mechanisms and platform capabilities, but they are not neutral comparisons of RDMA, SmartNICs, and computational storage. NVIDIA’s GPUDirect page advertises “10X better performance” for GPUDirect RDMA without benchmark conditions alongside the claim. Treat that as NVIDIA’s marketing statement, not as a general result that applies to every workload.
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A practical evaluation checklist
- Trace the current pipeline from storage read to accelerator input and identify where time, CPU cycles, copies, and bytes accumulate.
- Define one bottleneck and one success metric, such as host CPU time per batch, network-transfer latency, storage bytes delivered to the host, or accelerator idle time.
- Check hardware, firmware, driver, runtime, fabric, and API compatibility for the proposed path.
- Prototype the smallest change: RDMA for a measured transfer, a SmartNIC/DPU offload for one infrastructure service, or one computational-storage operation.
- Measure end-to-end behavior under representative concurrency and failure conditions, not only a device-level throughput number.
- Include operational costs: firmware and software maintenance, monitoring, security review, staff skills, and recovery procedures.
- Keep a conventional fallback path where practical so an unavailable offload device or unsupported data type does not stop the workload.
Bottom line
RDMA improves the path by moving data with less host-CPU involvement. SmartNICs and DPUs improve the path by taking infrastructure services off the host and, in some designs, isolating them. Computational storage improves the path by processing selected data before it travels onward. Treat them as separate levers, measure the actual bottleneck, and deploy only the lever whose requirements and operational trade-offs fit the workload.
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