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2D semiconductors are not missing from commercial chips because a single transistor cannot work. Laboratory devices made from atomically thin transition-metal dichalcogenides (TMDs) can show excellent electrostatic control, high on/off ratios and competitive switching metrics. The barrier is manufacturing a complete, repeatable CMOS-compatible process across an entire wafer, with acceptable defect rates, contact resistance, polarity control, thermal budget, yield and long-term reliability.
That distinction explains why 2D channels remain a serious option for future scaling but are not yet a broad replacement for silicon in mass-produced logic. A chipmaker must manufacture millions or billions of devices that behave predictably, not just demonstrate one exceptional transistor.
What “manufacturable” means for a 2D transistor
A transistor demonstration answers whether a material can switch current. A commercial process must answer a much longer list of questions:
- Can the semiconductor be formed with nearly the same thickness, composition and crystal quality over a full wafer?
- Can every layer be patterned, contacted and insulated without damaging an atomically thin channel?
- Do n-type and p-type devices have stable, controllable thresholds for CMOS logic?
- Can the process stay within the temperature, contamination and alignment limits of a real fab?
- Do device parameters remain within a narrow distribution from die to die and wafer to wafer?
- Does the circuit continue to work after electrical stress, temperature cycling and years of operation?
The 2024 IEEE International Roadmap for Devices and Systems (IRDS) summarizes the central problem this way: “The state-of-the-art electronic properties of TMD FETs, as well as their yield, variability, and reliability, may be further enhanced if progress is achieved in mainly five directions: channel fabrication, doping, source/drain contact resistance, gate dielectric, and variability.” Those areas are tightly coupled; improving one can make another harder to control.
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Wafer-scale growth still brings non-uniform material
Coverage is not the same as a usable channel
Chemical vapor deposition (CVD) and molecular beam epitaxy (MBE) can create large-area TMD films, but a continuous-looking film does not guarantee uniform transistor behavior. A production wafer needs consistent atomic-layer thickness, composition, crystal orientation and defect density. Even a one-layer difference can alter the channel’s threshold voltage, band structure and resistance.
The 2026 National Science Review manufacturing review identifies thickness variation, grain boundaries and vacancies as defects that reduce mobility and reliability. They also produce within-wafer and wafer-to-wafer variation, which directly lowers circuit yield. A wafer may therefore be fully covered yet still contain regions that require different operating voltages or deliver substantially different current.
Grain boundaries and crystal orientation
Large-area films usually grow from many nuclei. Where domains meet, a grain boundary can introduce scattering or trap charge. Domains with different crystal orientations create additional boundaries and uncontrolled transport paths. The IRDS review notes that many single-crystal demonstrations use micrometre-scale crystals, while wafer-level single-crystal quality is rarely obtained in the reported work. That gap matters because a circuit cannot be designed around isolated microscopic regions of perfect crystal.
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Transfer and direct growth solve different problems
Transferred films: cleaner growth, dirtier integration
Many high-performing 2D devices are grown on a substrate that provides favorable chemistry and then moved to the target wafer. Transfer separates material synthesis from transistor fabrication, which can improve crystal quality, but it adds alignment, handling and cleaning steps.
Polymer scaffolds used in transfer can leave residues or introduce impurities at the channel and contact interfaces. Wrinkles, tears, trapped particles and local strain produce further variation. The IRDS describes transfer as slow and a source of variability, so a method that works for a small number of devices is not automatically suitable for high-throughput wafer processing.
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Direct growth: fewer transfers, harder thermal control
Growing the TMD directly on a CMOS-processed silicon wafer could remove transfer-related residue and alignment problems. One approach described by the IRDS uses a two-temperature-zone CVD or metal-organic CVD process: the chemistry is generated at a higher temperature while deposition occurs at a lower temperature near the CMOS wafer.
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However, the lower-temperature surface must still produce a uniform, electrically active film without contaminating completed circuitry. In the cited direct-growth-on-CMOS-wafer example, the maximum reported on-state current was about 3 µA/µm. A separate leading MoS2 demonstration reported 1.23 mA/µm at 1 V drain-source bias. These are different device demonstrations, not a controlled comparison or a universal performance ratio; together they illustrate the integration-versus-performance gap that direct growth still has to close.
Future approaches include selective-area growth, wafer bonding and automated transfer. These are integration directions under development, not evidence of volume-qualified production.
Contacts remain a central bottleneck
Why a good channel can still deliver little current
The metal–semiconductor interface can dominate a 2D transistor’s resistance. Carrier-injection barriers and contact resistance reduce on-current, slow switching and make the measured result sensitive to contact geometry. Because the channel is only an atom or a few atoms thick, conventional three-dimensional metal contacts do not automatically form an ideal low-resistance interface.
Semimetals, edge contacts and van der Waals interfaces have improved laboratory results. Yet a manufacturable contact must combine low resistance with short length, tight dimensional control, clean processing and compatibility with subsequent thermal steps. A contact that is excellent when several micrometres long may not retain that performance when scaled to a logic node.
Scaled geometry changes the comparison
A 2024 National Science Review perspective reports a 42 Ω·µm contact-resistance result for an antimony (Sb) contact on monolayer MoS2. That is an important device result, but it does not by itself establish an integrated-circuit solution. The same perspective notes that some low-resistance demonstrations use micrometre-scale contact lengths, while an advanced-node IRDS requirement calls for a contact length below 20 nm. The roadmap figure is a target, not a measured industry-wide production value.
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At short lengths, current crowding, interface roughness, lithographic edge placement and contact-induced doping become more significant. Contact resistance must therefore be reported with the actual contact dimensions and process sequence, not as a standalone champion number.
CMOS needs controllable complementary polarity
Why n-type-only demonstrations are insufficient
Modern logic normally uses complementary metal-oxide-semiconductor (CMOS) circuits: n-type and p-type transistors work together to reduce static power. The IRDS review says larger-scale demonstrations in its survey have leaned toward n-type MoS2, while true complementary integration remains limited.
A usable p-type device needs a stable source of holes, a predictable threshold voltage, acceptable mobility and a process that does not damage the n-type device. Those requirements must hold over the wafer, not just in selected test structures. If one polarity varies more than the other, inverter noise margins, timing and standby power all become difficult to guarantee.
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Charge-transfer doping has shifted thresholds and increased current in reported examples. It can also make a transistor fail to turn off if the dopant concentration is too high. The process must control dose, placement, activation and stability during later fabrication and operation.
Contact engineering further complicates terminology. A metal can favor injection of electrons or holes and make a device appear more n-type or p-type without permanently doping the channel. Selecting a contact metal alone therefore does not solve stable, manufacturable CMOS polarity control.
Gate dielectrics, spacers and interfaces must work together
Atomically thin channels expose interface problems
Because a 2D channel has no bulk material to screen nearby charges, the gate dielectric interface strongly affects its threshold voltage, mobility and reliability. Traps, residues, roughness and fixed charge can scatter carriers or cause hysteresis. Dielectric deposition can also damage the channel or create a non-uniform nucleation layer.
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The 2024 perspective lists dielectric integration and spacer design among unresolved issues. The 2026 review adds interface states, dielectric-polarization impurities and passivation as concerns. A production gate stack must provide strong electrostatic control while avoiding traps and maintaining that behavior after thermal cycling.
Spacers and low-k materials are not optional details
Source/drain spacers set electric-field profiles, parasitic capacitance and the distance between the gate and contacts. Conventional spacer materials and deposition temperatures may not be compatible with an atomically thin TMD or with a back-end-of-line (BEOL) flow. The 2026 review specifically identifies the lack of compatible low-k spacer processes as an open issue.
Passivation must protect the surface from oxygen, moisture and processing chemicals without introducing new charge traps. These interface choices affect both the initial transistor result and whether the threshold remains stable over time.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.CMOS process compatibility limits the thermal and chemical budget
A 2D material can be attractive at the device level yet unusable if it requires temperatures or chemicals that destroy completed silicon circuitry. The 2026 review lists thermal budget, contamination control, lithographic alignment, metallization compatibility and reliability as system-level requirements.
For that reason, proposed BEOL-compatible routes often target processing below 400 °C. This is a process direction discussed in the review, not a universal demonstrated threshold for every 2D material, dielectric or contact. A fab must also prevent TMD precursors, dopants and polymer residues from contaminating tools used for other products.
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Variability, yield and reliability determine whether a chip is sellable
From a champion device to a wafer map
Commercial readiness requires distributions, not a best value. Manufacturers need across-wafer maps of threshold voltage, mobility, contact resistance, leakage and breakdown, plus wafer-to-wafer and lot-to-lot statistics. They also need defect inspection, parametric outlier rates and circuit-level yield.
The currently reviewed literature identifies these measurements as necessary but does not provide a comparable contemporary data set for production-compatible 2D process modules. That evidence gap is itself significant: without common wafer-scale statistics, it is impossible to compare a transfer flow with a direct-growth flow fairly.
Reliability must survive the whole product life
Reliability testing must examine bias-temperature stress, hot-carrier or high-field effects, dielectric breakdown, contact degradation, threshold drift and environmental exposure. Vacancies, interface traps and mobile contaminants can evolve during operation, so an initially strong transistor may lose performance or fail to switch at its designed voltage.
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Reported laboratory metrics can still be impressive. The transferred MoS2 device summarized by the 2024 IRDS achieved 1.23 mA/µm on-state current at 1 V drain-source bias, an intrinsic delay of 74 femtoseconds and an on/off ratio above 108, using an HfO2 gate dielectric. Those values describe that device study; they are not production-fab results and do not include a demonstrated wafer-scale yield or lifetime.
How the main integration routes compare
| Integration route | Potential advantage | Manufacturing risk that remains |
|---|---|---|
| Transfer from a growth substrate | Can use growth conditions that produce high-quality TMD crystals | Polymer residue, wrinkles, tears, particles, slow handling and alignment variability |
| Direct growth on processed CMOS wafers | Avoids some transfer steps and may improve alignment | Low-temperature nucleation, film uniformity, contamination and lower demonstrated current in the cited example |
| Wafer bonding | Separates material growth from the CMOS thermal budget | Bond quality, interface cleanliness, alignment and defect propagation across the wafer |
| Selective-area growth | Places material only where devices are needed | Pattern dependence, edge defects, precursor selectivity and repeatability |
No route wins on a single metric. A meaningful comparison must include defect density, crystal uniformity, residue, thermal compatibility, contact resistance at realistic dimensions, complementary polarity, dielectric and spacer quality, yield and reliability.
What would count as convincing commercial readiness?
A credible claim that 2D logic is ready for broad manufacturing would need a defined fab flow and evidence such as:
- Uniform film thickness, composition and defect statistics across full wafers.
- Repeatable transfer or direct-growth steps with controlled contamination and alignment.
- Contact resistance demonstrated at the intended contact length, not only with long laboratory contacts.
- Stable n-type and p-type devices with matched thresholds and useful noise margins.
- Gate dielectric, spacer and passivation modules that meet leakage, capacitance and reliability targets.
- Wafer maps, lot-to-lot distributions, circuit yield and reproducible process control.
- Accelerated lifetime data showing stable thresholds, contacts and dielectrics.
Roadmaps illustrate the scale of the challenge. The IRDS projection cited by the 2024 National Science Review perspective places a 0.7 nm node in 2034. That is a roadmap projection, not a guarantee and not evidence that commercial 2D chips will exist by that date.
Why silicon has not been replaced yet
Silicon benefits from decades of optimized crystal growth, oxidation, doping, lithography, contact formation, contamination control and statistical process engineering. A 2D channel can offer excellent electrostatics at very small dimensions, but it must be inserted into that mature manufacturing ecosystem without losing its material advantages.
The unresolved problems are therefore less about proving that a TMD transistor can switch and more about making every surrounding module predictable. Until wafer-scale uniformity, contacts, complementary doping, gate stacks, thermal compatibility, yield and reliability are demonstrated together, 2D semiconductors remain a promising future-integration option rather than a broad commercial logic technology.
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