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Advanced AI chips are made through a long chain of design, wafer fabrication, packaging and testing—not a single printing operation. Engineers define the architecture, a fab builds hundreds of microscopic layers on silicon wafers, and specialist assembly lines turn tested dies into electrically connected packages that can combine compute with high-bandwidth memory. ASML says the overall journey can involve hundreds of steps and take up to four months from design to mass production, although cycle time varies by product and factory.
What “manufacturing an AI chip” actually includes
An AI accelerator becomes a shippable product only after several distinct operations:
- Architecture and circuit design: engineers define compute units, memory interfaces, interconnects, power delivery and software-facing features.
- Process planning: the design is mapped to a specific semiconductor process, design rules and manufacturing partners.
- Wafer fabrication: a fab builds transistors and wiring by repeatedly depositing, patterning, etching and modifying thin films on silicon.
- Wafer inspection and yield control: measurements identify defects and process drift before usable dies are separated.
- Assembly and advanced packaging: dies are connected to substrates, interposers, redistribution layers or other dies, often alongside high-bandwidth memory.
- Final test: packaged parts receive electrical, thermal and functional checks before shipment.
Skipping any of these stages gives a misleading picture. A wafer full of transistor patterns is not yet an AI processor, and a fabricated die is not a usable product until it can be powered, cooled, connected and tested in its package.
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Defining the AI workload
Design teams first decide what the processor must accelerate. Training and inference workloads influence the number and type of matrix engines, vector units, caches, on-chip memory, external-memory interfaces and high-speed links. Power limits, cooling assumptions and the target system determine how much computation can fit in one die and whether several dies should be combined.
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Turning architecture into physical circuitry
Logical blocks are converted into transistor-level circuits and then into physical layouts. The layout specifies the geometric shapes that will eventually be patterned on the wafer. It also has to obey the chosen process’s spacing, wiring, voltage and reliability rules. Verification checks include functional behavior, timing, power, signal integrity and manufacturability.
Choosing the manufacturing model
A fabless company concentrates on design and contracts production. ASML cites Qualcomm, Nvidia and AMD as examples of fabless companies. A foundry manufactures chips for customers; ASML uses TSMC as an example. An integrated device manufacturer designs and manufactures its own chips. These business models can overlap in practice, but the distinction explains who owns the design, who operates the fab and who controls packaging or testing.
Process selection is more than choosing a number such as “3 nm” or “18A.” The design team selects a complete technology platform: transistor structure, available libraries, memory options, interconnect rules, lithography strategy, packaging support and qualified design tools. A process name alone does not identify every layer, tool or packaging method used in the finished AI product.
2. Preparing the silicon wafer and building thin films
Starting with a polished wafer
Manufacturing begins with extremely flat, high-purity silicon wafers. A 300-millimeter wafer, commonly called a 12-inch wafer, holds many copies of a die layout. The wafer is cleaned and prepared so that subsequent films adhere evenly and contamination stays within strict limits.
Depositing material layers
Fabs deposit thin films that may be conductive, insulating or semiconductor materials. The exact stack changes throughout the process. Some films become transistor channels, gates or contacts; others isolate neighboring structures or form the many levels of metal wiring that carry power and data. Deposition methods are selected for thickness control, uniformity and compatibility with the underlying layer.
Because features are built vertically as well as horizontally, surface preparation matters. Cleaning, planarization and thermal treatments keep the wafer flat and control the electrical properties of each layer. A tiny defect or thickness variation can affect many dies, so equipment operates inside tightly controlled environments.
3. Patterning each layer with lithography
Coating the wafer with photoresist
The wafer receives a photosensitive material called photoresist. A reticle, which carries the intended circuit pattern, is aligned with the wafer. Lithography projects light through the reticle and into the resist. Exposure changes the resist’s chemical behavior in selected regions.
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Baking and developing the pattern
After exposure, controlled baking and chemical development leave openings in the resist. Depending on the resist type, either the exposed or unexposed regions are removed. The resulting pattern is a temporary stencil that defines where the underlying film will be altered.
Etching and material modification
Etching removes exposed portions of the film through dry plasma or wet chemical processes. Ion implantation can introduce carefully selected atoms into silicon, changing its conductivity and helping form transistor source, drain and other regions. Additional cleans, anneals and surface treatments refine the result. The remaining resist is stripped before the next operation.
Each lithography exposure covers only a particular layer and area. Alignment systems register the new pattern against structures already on the wafer. Overlay error, line-edge roughness, incomplete etching and particle contamination are among the problems engineers monitor.
4. Repeating the cycle hundreds of times
Fabrication is a sequence, not a single pass. A simplified cycle looks like this:
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- Clean and prepare the wafer surface.
- Deposit a conductive, insulating or semiconductor film.
- Apply and bake photoresist.
- Align a reticle and expose the resist with the selected lithography tool.
- Develop the resist to reveal openings.
- Etch, implant or otherwise modify the exposed material.
- Strip the resist, clean the wafer and measure the result.
- Repeat for the next layer until transistors, contacts and interconnects are complete.
Modern logic devices require many patterned layers. Some define the transistor’s finest features; others create contacts and progressively larger wiring levels. Memory products use their own repeated structures and process sequences. The exact number of operations depends on the technology and product, so “hundreds of steps” is a general description rather than a universal count.
5. EUV and DUV: different tools for different layers
Extreme ultraviolet (EUV) lithography uses light with a 13.5-nanometer wavelength. ASML describes its NXE EUV systems as tools for advanced logic and memory production. EUV can pattern some of the most intricate layers with fewer multiple-patterning operations than older approaches.
Deep ultraviolet (DUV) lithography remains important. Not every layer needs EUV resolution, and fabs may use DUV tools for larger features or for layers where that approach is technically and economically appropriate. An advanced chip can therefore contain layers made with both EUV and DUV, along with etch, deposition and metrology equipment from many suppliers.
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| Aspect | EUV | DUV |
|---|---|---|
| Light source | 13.5 nm wavelength, as specified by ASML for its EUV systems | Longer ultraviolet wavelengths used across a range of established processes |
| Typical role | Some of the most intricate advanced-logic and memory layers | Other critical layers and processes where its resolution and cost are suitable |
| Relationship in a fab | Works alongside DUV, deposition, etch and measurement systems | Remains part of leading-edge as well as mature-layer production |
ASML lists a 0.55 numerical aperture for its next-generation EXE High NA platform. In a July 15, 2026 release, ASML reported that Intel Foundry was using EXE High NA EUV on Intel 18A to produce a subset of Intel Core Ultra Series 3 processors in high-volume manufacturing. The company said specified layers had been dual-qualified and that the product was shipping at yields matched to the NXE platform. This is a dated, company-reported milestone for one product and process; it does not mean that all advanced AI chips use High NA EUV.
6. Inspection, metrology and yield management
Finding defects and drift
Inspection systems search for particles, scratches, missing features and pattern defects. Metrology measures dimensions such as critical linewidth, film thickness, overlay and electrical properties. Measurements are collected after key steps rather than waiting until the end, when correcting a problem would waste an entire wafer.
Using feedback to stabilize the process
Fab-control software compares measurements with targets and adjusts exposure, focus, dose, temperature, gas flow, etch time or deposition conditions. Engineers also trace defects to equipment, materials and wafer locations. Statistical process control helps distinguish normal variation from a developing failure.
Why yield matters for AI accelerators
Yield is the fraction of manufactured dies that meet specifications. A defect can disable one die, reduce its performance grade or make the wafer unusable. Large AI dies are especially sensitive because their physical area gives defects more opportunity to land inside a critical region. Designers may include redundancy, disable faulty units or create multiple product grades, but those techniques do not eliminate the cost of low yield.
7. Wafer sort and die separation
Before packaging, electrical probing checks dies while they are still on the wafer. Test data identifies which dies meet voltage, frequency, memory and connectivity requirements. The wafer is then thinned when required, mounted for separation and singulated into individual dies by saw, laser or another qualified method.
Known-good-die information is valuable when several dies will be placed in one package. Combining an untested or marginal die with expensive memory and an interposer creates avoidable risk, so assembly planning uses wafer-sort results and traceability data.
8. Why advanced packaging is part of the AI chip
More than a protective shell
In advanced computing, packaging provides mechanical protection and electrical connections while also solving bandwidth, power and heat problems. Fine-pitch interconnects, redistribution layers, interposers, substrates, underfill and thermal interfaces all affect whether the finished device can operate at its intended speed.
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2.5D integration with high-bandwidth memory
TSMC describes CoWoS as a 2.5D platform that integrates multiple system-on-chip dies and high-bandwidth memory for high-performance computing and AI. An interposer or similar routing structure places compute dies and memory close together, creating wide connections without requiring every function to fit on one enormous monolithic die.
3D stacking and other approaches
TSMC also describes SoIC for three-dimensional stacking and InFO among its advanced packaging technologies. In a 3D arrangement, dies can be stacked vertically with very short interconnects, but the design must manage alignment, heat removal, power delivery, mechanical stress and test access. Different products use different combinations of monolithic dies, chiplets, interposers and stacked memory.
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AI workloads can draw substantial power for long periods. The package must move heat from the die into a heat spreader or cooling system while maintaining reliable solder joints and fine-pitch connections. Warpage, thermal-expansion mismatch and mechanical stress can damage a package or reduce lifetime, so packaging is co-designed with the die and the system board.
9. Assembly and final testing
Intel’s assembly-and-test overview describes a package as providing protection, strength and electrical connections. The general flow can include die attach, interconnect formation, encapsulation or underfill, substrate attachment, lid or heat-spreader installation, marking and inspection. Multi-die products add alignment and connection steps for each component.
Packaged chips then undergo several classes of test:
- Electrical tests: confirm power rails, interfaces, memory links, leakage and operating limits.
- Functional tests: run logic and workload patterns to detect defective compute units or connections.
- Speed and power grading: sort parts into performance bins based on measured frequency, voltage and consumption.
- Thermal and reliability tests: expose samples or production parts to temperature, voltage and mechanical conditions appropriate to the qualification plan.
- Visual and package inspection: check solder, molding, warpage, markings and other physical characteristics.
Only after fabrication, assembly and the required test flow are complete does a die become a shippable AI processor. System-level testing may continue after shipment as manufacturers validate boards, firmware, cooling and software stacks.
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ASML says semiconductor manufacturing involves hundreds of steps and can take up to four months from design to mass production. That statement is a general explanation from ASML, not a guaranteed cycle time for every AI product or fab. Design verification, mask preparation, pilot lots, process qualification, yield learning, packaging capacity and customer testing can each add time.
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Production also operates at enormous wafer scale. TSMC reported 15.0 million 12-inch-equivalent wafer shipments in 2025 and said 74% of its wafer revenue came from advanced technologies of 7 nm and beyond. Those are TSMC’s company-reported totals and revenue mix for that year, not measurements of the entire semiconductor industry or of AI chips alone.
11. Energy, chemicals and the limits of simple per-chip claims
Chip manufacturing consumes electricity, water and wet chemicals across wafer processing, cleanroom operation, gas handling, cooling and packaging. A single universal water, emissions or cost number per AI chip would be misleading because die size, wafer yield, process complexity, fab location, energy mix, packaging and test volume all vary.
ASML’s 2025 annual-report feature on the imec.netzero model compares technologies introduced between 2013 and 2025 at the process level. Under the model’s assumptions, EUV single patterning can mean around 20% fewer process steps per wafer than DUV multi-patterning, and modeled operational emissions (scope 1 and 2) may be approximately 10% lower. These are scenario results whose emissions outcome depends on the stated assumptions, not guaranteed savings for every fab or chip.
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The model’s value is its level of detail: it can compare process steps, electricity per wafer and wet-chemical use per wafer, helping engineers identify high-impact operations. It should not be converted into a blanket environmental claim about all EUV products.
12. How to interpret a manufacturing claim
When a company announces a new AI chip or process, check six points before drawing a conclusion:
- Process status: distinguish a technology demonstration, risk production, qualification, pilot line or high-volume manufacturing.
- Exact date and geography: note when and where the claim was made, because fab ramps and tool availability change.
- Lithography scope: identify which layers use EUV, DUV or multiple patterning; a process label does not answer this by itself.
- Packaging and memory: determine whether the product uses monolithic integration, chiplets, an interposer, 3D stacking or high-bandwidth memory.
- Yield definition: ask whether the figure covers raw die yield, a particular product grade, a qualified layer or a company-wide average.
- Source type: separate a vendor announcement from an independent measurement or neutral cross-company comparison.
Company reports are authoritative for that company’s own specifications, production milestones and financial totals, but they should retain their stated scope. The available evidence does not establish a neutral ranking of foundries by cost, performance or total yield.
The essential idea
An advanced AI chip is the result of a linked manufacturing system. Design determines the circuits and constraints; repeated deposition, lithography, development, etching, implantation, cleaning and measurement create those circuits on a wafer; yield control separates usable dies from defects; and advanced packaging connects compute with memory while handling heat and mechanical stress. Assembly and electrical, thermal and functional testing complete the transformation from microscopic patterns into a dependable product.
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