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Scaling a silicon quantum processor means building a complete semiconductor system in which thousands or millions of physical qubits can be fabricated with consistent characteristics, tested at cryogenic temperature, controlled with a manageable number of signals, connected for error correction, and cooled without disturbing operation. Making a larger prototype chip is not enough.
The essential requirements are high-yield CMOS-compatible fabrication, wafer-scale cryogenic testing, uniform high-fidelity qubits, local cryogenic control and readout, dense low-loss packaging, an error-correction-compatible connectivity scheme, and modular links between processor tiles. Research has demonstrated important pieces, but no source establishes a commercially useful, fault-tolerant silicon system that integrates all of them at scale.
What “scaling” means for a silicon quantum processor
A prototype can succeed by selecting a few exceptional devices, routing a large number of wires to them, and tuning each qubit manually. A useful processor cannot rely on that approach. Scaling requires the same process to produce many working qubits, characterize them quickly, operate them simultaneously, and replace or isolate defects without collapsing the computer’s error-correction scheme.
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1. High-yield, low-variation fabrication
Why yield becomes the first-order constraint
In an early experiment, engineers may fabricate many devices, cool them one at a time, and keep only the dots or gates that meet specifications. In a large array, every missing, unstable or badly tuned component reduces usable connectivity and complicates calibration. Yield therefore means more than the percentage of dies that power on: gate dimensions, tunnel barriers, charge noise, valley splitting, sensor response and wiring must all fall inside operating windows.
The Nature wafer study on silicon devices reports low-disorder silicon/germanium processing, full-wafer cryogenic probing and automated single-electron measurements. Its central scaling lesson is that the next order of magnitude needs higher component yield and more efficient testing, because screening a large population for a small number of good devices does not scale economically or architecturally.
CMOS compatibility helps, but does not guarantee millions of qubits
CMOS-compatible fabrication provides established lithography, deposition, etching, metrology and process-control infrastructure. It also makes it possible to add more interconnect layers and to pursue two-dimensional arrays using techniques familiar from semiconductor manufacturing. However, a quantum process has additional requirements: extremely low disorder, stable electrostatic potentials, reproducible interfaces and low defect densities at cryogenic temperature. A process can be geometrically uniform at room temperature while still producing qubits with widely different behavior when cooled.
Intel reported a 300-millimeter cryogenic-probing process using all-CMOS-industry manufacturing and a 99.9% gate fidelity for the single-electron devices in that report. That number is an important device result, not evidence that a complete million-qubit processor has been built. Reaching that scale still requires the same quality across a very large population, reliable interconnect layers and a way to route and control two-dimensional arrays.
Process control must be statistical
At prototype scale, engineers can correct variation by hand. At wafer scale, manufacturing must track distributions: threshold voltages, charging energies, barrier settings, sensor gains, leakage and defect rates. Statistical process control is needed to identify drift between wafers and lots, while design rules must tolerate the remaining spread. The National Academies has warned that millions of qubits will require advanced process monitoring and defect reduction, not just incremental improvements to isolated devices.
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2. High-throughput cryogenic testing before packaging
Why conventional testing is too slow
A conventional workflow cools one packaged device, measures it, warms it, dices another die, bonds it and repeats the thermal cycle. That sequence adds handling, wiring and cryostat time for every sample. It also hides wafer-level variation until late in the process, when correcting a fabrication problem is expensive.
Full-wafer probing at about 4 K
The reported wafer-scale approach places a wafer or a large wafer section in a cryogenic probe system at temperatures at or below approximately 4 K. Automated instruments then measure many devices and extract characteristics such as single-electron addition behavior, charge stability and gate response. The resulting data reveal whether a process is improving across the wafer and whether a device family is suitable for array integration.
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3. Control and readout without an impossible wire count
The one-wire-per-qubit problem
Every qubit needs signals for initialization, manipulation and measurement, but a dilution refrigerator has limited space, cooling power and connector capacity. Room-temperature instruments connected by individual coaxial cables create the familiar “rat’s nest” of wires. The National Academies identifies local control logic, three-dimensional or monolithic integration and cryogenic operation of some electronics as requirements once systems exceed roughly a thousand qubits.
Moving electronics closer to the qubits reduces long cables, yet those circuits dissipate heat. The design must place each function at a temperature stage where its power can be removed without warming the qubit plane. Electronics at 4 K have substantially more cooling capacity than the coldest stage, but signals still have to cross the final wiring bottleneck to the base-temperature chip.
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What the SpinBus estimate shows
The SpinBus architecture gives a concrete accounting for a two-dimensional silicon-spin array. For N unit cells, it specifies 15N + 4 AC signals and 3N + 4 DC signals under its control assumptions.
| Quantity | SpinBus estimate | Scaling implication |
|---|---|---|
| AC signals | 15N + 4 | High-frequency control and readout lines grow with the number of unit cells. |
| DC signals | 3N + 4 | Bias and tuning lines also grow, even when some functions are shared. |
| Practical cable limit in the estimate | About 1,000 coaxial cables | The cryostat, connectors and thermal load impose a physical ceiling. |
| Array represented under those assumptions | About 72 two-qubit unit cells, or 144 simultaneously operable qubits | Multiplexing and local electronics are needed for a much larger processor. |
The exact numbers depend on architecture and operating assumptions, but the principle is general: adding qubits while preserving one dedicated line per function eventually exhausts the refrigerator. A scalable design shares control resources, stores settings locally, multiplexes measurements or moves signal generation into a cryogenic stage.
Superconducting and mixed-signal control
NIST describes superconductive microwave and mixed-signal circuits as ways to replace part of the room-temperature wiring. In a 2023 single-qubit demonstration using single-flux-quantum control, NIST reported gate fidelities greater than 99.5%. Such demonstrations show that cryogenic control can preserve high operation quality; they do not by themselves establish the power budget, calibration method or reliability needed for a large silicon array.
4. High and uniform qubit fidelity
Why averages are not enough
Error correction consumes many physical qubits to create one logical qubit. A processor therefore needs not only a high average fidelity but also a narrow distribution, predictable drift and a low rate of unusable components. A few weak links can force the compiler to avoid parts of the array or can lower the threshold margin for an entire code block.
Error-rate targets for practical correction
The National Academies identifies physical-qubit error rates in the 10−3 to 10−4 range as a key target for practical quantum error correction. Silicon experiments have reported fidelities above 99%, including the 99.9% gate-fidelity figure in Intel’s reported single-electron devices. Fidelity and error rate are related but not interchangeable across experiments: the measured operation, leakage definition, calibration protocol and noise model matter.
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Scaling therefore requires repeatable two-qubit operations, measurement fidelity, reset, leakage control and long-duration stability. A headline single-qubit result is necessary evidence of progress, but it is not a complete error-correction qualification.
5. Connectivity designed for error correction
Geometry must match the code
A useful array cannot be a random collection of excellent qubits. Neighbor relationships, routing paths and measurement zones must support the chosen error-correcting code. SpinBus uses a two-dimensional arrangement suited to surface-code operations and proposes moving electrons between manipulation zones. Its authors state that predicted fidelities are in the range needed for reasonable logical-qubit performance while emphasizing that the wiring must remain compatible with the cryostat, package and back-end-of-line manufacturing.
Shuttling and interaction zones
Separating storage, manipulation and readout zones can reduce the number of dedicated control elements per qubit, but shuttling introduces its own error channels. Electrons must move without losing spin information, accumulating unacceptable phase error or becoming trapped. A scalable architecture must demonstrate these movements repeatedly across many sites, not only in a carefully selected pair of devices.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.6. Packaging, thermal management and vertical interconnects
Keeping control electronics from heating the qubits
Control circuits generate heat, while the qubit plane operates at the coldest stage of a cryostat. Packages therefore need defined thermal paths, low-loss microwave transitions and isolation structures that prevent electrical and vibrational disturbances from reaching sensitive devices. SpinBus discusses phononic thermal isolation, superconducting vias and operation of electronics at a higher cryogenic temperature as possible solutions.
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Planar routing alone consumes valuable chip area and leaves too many signals at the perimeter. Through-substrate vias, flip-chip bonding, additional metal layers and superconducting vertical interconnects can move signals through the stack. Each option introduces fabrication tolerances, parasitic capacitance, thermal paths and reliability questions. The package must be characterized as part of the quantum system, because a qubit that works on a probe station can fail after bonding, thermal cycling or integration with active electronics.
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7. Modular processor tiles instead of one endlessly larger die
IBM’s 2023 scaling summary states that processors cannot continue to grow simply by increasing chip size. Large dies have lower yield, longer signal paths and more difficult thermal and mechanical constraints. A practical system is therefore likely to combine multiple processor tiles with high-density links.
Modularity changes the engineering target. Each tile needs local control, calibration and error-detection capability, while the inter-tile link must preserve synchronization and deliver sufficiently low error. Advanced packaging, flexible superconducting cables, through-substrate vias and cryogenic infrastructure become system components rather than optional accessories. Tile boundaries must also be considered by the error-correction layout; a link that is electrically possible but too noisy or slow can become a logical bottleneck.
8. How to judge whether a scaling claim is meaningful
When comparing silicon-spin processor proposals, evaluate the complete stack rather than qubit count alone.
| Evaluation axis | Questions to ask |
|---|---|
| Fidelity and uniformity | Are single- and two-qubit errors reported separately? How wide is the distribution across devices and repeated runs? |
| Fabrication yield | What percentage of components meet specifications without hand selection, and are defect types identified? |
| Cryogenic metrology | Were many devices measured automatically at wafer scale, or only a few packaged samples? |
| Control-line count | How does the number of signals grow with qubit count, and which functions are multiplexed or local? |
| Power and temperature | Where are amplifiers, waveform generators and memory located, and what is their heat load at each stage? |
| Error-correction connectivity | Does the physical layout support the intended code, measurement schedule and movement operations? |
| Package density | Are vertical interconnects, microwave transitions and thermal isolation demonstrated together? |
| Modularity | Can multiple tiles be linked without sacrificing synchronization, fidelity or calibration access? |
| Reproducibility | Are results shown across a wafer, multiple wafers or only one best-performing device? |
9. A realistic path beyond prototype size
- Standardize the device process. Establish low-disorder silicon/silicon-germanium fabrication with measured distributions for gates, barriers, sensors and interfaces.
- Measure at wafer scale. Use automated cryogenic probing near 4 K to collect enough data to tune process steps and identify defects before dicing and packaging.
- Demonstrate repeatable arrays. Move from isolated high-performing qubits to two-dimensional arrays in which most sites meet the operating window and can be calibrated by software.
- Integrate local control. Add multiplexers, memory, waveform generation and readout electronics at an appropriate cryogenic stage while keeping the base-temperature heat load within the refrigerator’s budget.
- Prove the package. Combine flip-chip or vertical interconnects, superconducting vias, microwave-compatible materials and thermal isolation through repeated thermal cycles.
- Run error-correction primitives. Demonstrate the required two-qubit gates, reset, measurement, leakage handling and connectivity in the intended code geometry.
- Connect tiles. Use modular links and packaging that preserve the same control, timing and error-rate margins across multiple processor dies.
What has been demonstrated—and what remains open
Research has demonstrated CMOS-compatible silicon devices, 300-millimeter wafer processing, automated cryogenic measurements, gate fidelities above 99%, cryogenic-control circuits and architectural proposals that address wiring and two-dimensional connectivity. Those results establish credible building blocks.
They do not yet establish a commercially useful, fault-tolerant silicon quantum computer. No reviewed source provides a date for such a system, and the integration problem remains open: manufacturing yield, statistical testing, control power, package density, thermal management, connectivity and error correction must all work at once. The defining milestone will be a reproducible, modular system whose physical-qubit quality and control infrastructure scale together, rather than a larger prototype containing a few exceptional devices.
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