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HBM4 is the fourth generation of High Bandwidth Memory: vertically stacked DRAM packaged beside an AI accelerator or high-performance-computing processor. Through-silicon vias (TSVs), a base die and an unusually wide interface let the package move very large amounts of data in parallel. HBM4 is memory, not a processor, graphics card or plug-in RAM module.
Its purpose is to keep parallel compute units supplied with model parameters, activations and other working data. The exact result depends on the accelerator, software, workload, package and system design; a higher HBM4 specification is not a guaranteed model-speed multiplier.
What is HBM4?
High Bandwidth Memory (HBM) is a type of DRAM assembled as a three-dimensional stack. Instead of placing memory chips separately on a circuit board and connecting them through a comparatively narrow interface, manufacturers stack multiple thin DRAM dies vertically. Thousands of through-silicon vias carry electrical signals through the dies, while a base or logic die provides the connection to the processor package.
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HBM4 is not a standalone computer component
You cannot use HBM4 as a replacement for desktop DIMMs, a graphics card or a general-purpose upgrade module. The stack, base die, package connections and accelerator are engineered as one system. Availability is therefore discussed in terms of accelerator products, package designs and supplier sampling or shipments rather than retail memory kits.
How HBM4 works inside an AI accelerator
- Compute units request data. Matrix engines, vector units and other accelerator blocks need model parameters, activations, gradients or intermediate results.
- A memory controller schedules the requests. The accelerator’s controller selects locations in the HBM stack and coordinates reads and writes.
- The base die connects the stack to the package. This die provides the interface logic that links the vertically stacked DRAM to the accelerator’s package-level connections.
- Signals travel through TSVs. TSVs run through the stacked dies, allowing many signals to move between layers without routing every connection around the edge of each chip.
- A very wide interface transfers data in parallel. HBM4 uses 2,048 I/O connections in the supplier material described here. Moving many bits at once across a short package-level path produces high throughput.
The key design choice is width. A conventional memory system often seeks higher transfer rates over a narrower external bus. HBM instead combines a broad bus with stacked dies and close physical integration. The implementation details, clocking, package topology and achieved results vary by supplier and accelerator.
HBM4 bandwidth and capacity are different
Capacity is the amount of information the memory can hold. Bandwidth is the amount of information that can cross the interface each second. A stack can have more bandwidth without holding more data, and a larger-capacity stack does not automatically deliver proportionally higher bandwidth.
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How the interface width affects the number
A simplified bandwidth calculation multiplies the number of data connections by the signaling rate and divides by eight to convert bits to bytes. With 2,048 I/O connections operating above 11.0 Gbps, Micron’s stated interface corresponds to more than 2.8 TB/s per stack. This arithmetic explains the relationship between the specifications; it is not a universal rating for every HBM4 product.
How fast is HBM4 compared with HBM3E?
HBM4 comparisons must keep the stack height, capacity and measurement basis consistent. The supplier figures below are product specifications or company comparisons, not independent laboratory benchmarks.
| Metric | HBM4 information reported by suppliers | HBM3E comparison information |
|---|---|---|
| Interface width | 2,048 I/O connections, reported by Micron and Samsung | 1,024 I/O connections identified for the preceding generation by Samsung |
| Per-pin signaling | Micron: above 11.0 Gbps; Samsung: 11.7 Gbps consistent operation and up to 13 Gbps performance | Not stated in the reviewed supplier material |
| Bandwidth per stack | Micron: more than 2.8 TB/s; Samsung: up to 3,300 GB/s (3.3 TB/s) | Not stated as a single comparable value |
| Capacity in a 12-high stack | Micron: 36 GB; Samsung: 24 GB to 36 GB products | Micron compares its 36 GB 12-high HBM4 with a 36 GB 12-high HBM3E configuration |
| Higher stack option | Samsung describes up to 48 GB with 16-layer stacking as a planned expansion; Micron lists 48 GB 16-high customer samples in its timeline | Not stated in the reviewed supplier material |
The apparent difference between “more than 2.8 TB/s” and “up to 3.3 TB/s” is not a contradiction. They describe different suppliers’ implementations and operating points. Do not quote either figure as the universal speed of every HBM4 stack or of a complete accelerator.
Why AI accelerators use HBM4
AI training and inference are often limited by how quickly data can reach the compute engines. A training step may stream weights, activations, gradients and optimizer data repeatedly. Inference must fetch model parameters and process activation tensors for each request. When the memory system cannot supply data fast enough, some compute resources can wait instead of performing useful work.
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HBM4 is intended to reduce that data-supply bottleneck by providing high aggregate throughput next to the accelerator. It is particularly relevant when:
- Many processing units access large tensors concurrently.
- The workload repeatedly streams data rather than reusing a small working set in on-chip cache.
- The accelerator has enough arithmetic capacity that external memory traffic becomes the limiting factor.
- Large models require more memory than on-chip SRAM can provide.
More bandwidth does not guarantee a specific training-time or inference-time improvement. Software scheduling, kernel efficiency, interconnects, accelerator architecture, model sparsity, batch size and the number of HBM stacks all affect the result. A compute-bound workload may see little benefit from a faster memory interface, while a bandwidth-bound workload can benefit substantially.
Power, packaging and thermal considerations
Stacking increases the amount of memory connected in a small package, so the accelerator, package substrate, interposer and cooling solution must be designed together. Power delivery, signal integrity and heat removal are system-level concerns; a supplier’s per-stack figure cannot be translated directly into the power or temperature of a complete accelerator.
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SK hynix reported a greater-than-40% power-efficiency improvement over the previous generation on September 12, 2025. That is a company-reported comparison, not an independently verified result that applies to all HBM4 implementations. When evaluating products, ask what “efficiency” measures, which baseline was used and whether the comparison covers the memory stack alone or a larger system.
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HBM4 supplier status and dates
| Supplier and date | Reported development or product status | Reported figures |
|---|---|---|
| SK hynix, September 12, 2025 | Announced completion of HBM4 development and preparation of a mass-production system | 2,048-I/O design and operating speed above 10 Gbps, according to the company |
| Samsung Electronics, February 12, 2026 | Announced that HBM4 mass production had begun and that commercial products had shipped to customers | 11.7 Gbps consistent operation, up to 13 Gbps performance, up to 3.3 TB/s per stack, and 24 GB to 36 GB in 12-layer products |
| Micron, current product information accessed in 2026 | Lists a 36 GB 12-high product and 48 GB 16-high customer samples in its product timeline | More than 2.8 TB/s per stack from a 2,048-pin interface operating above 11.0 Gbps |
These announcements describe each company’s products and milestones available through October 13, 2026. Sampling, manufacturing, shipment status and specifications can change, so a buyer or system designer should verify the supplier’s current product documentation and the accelerator vendor’s qualification status.
“Completion of HBM4 development will be a new milestone for the industry,” said Joohwan Cho, Head of HBM Development at SK hynix, on September 12, 2025.
The quotation is a corporate statement about the company’s development milestone, not independent evidence of an industry-wide performance change.
How to read an HBM4 specification sheet
Numbers are meaningful only when their context is clear. Use this checklist when comparing HBM4 options or accelerator products:
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- Stack height: Compare 12-high with 12-high, or 16-high with 16-high. Height changes capacity and package characteristics.
- Capacity per stack and total capacity: Distinguish the amount in one stack from the amount across the complete accelerator.
- Bandwidth basis: Check whether the figure is per stack, per package or for an entire system.
- Pin speed and interface width: A higher per-pin rate and a wider bus both affect throughput, but they are not interchangeable specifications.
- Power-efficiency baseline: Ask whether a percentage compares identical capacities, workloads, stack heights and operating conditions.
- Thermal and package limits: Confirm the accelerator’s cooling and package design rather than assuming a memory-stack number predicts system temperature.
- Availability date: Separate announced development, customer samples, mass production and shipped commercial products.
What is known about the HBM4 standard?
SK hynix has described 8 Gbps as the standard operating speed and its own HBM4 as exceeding that figure. The material available for this explainer does not include the primary JEDEC HBM4 publication, so the exact normative wording, scope and operating limits have not been independently checked here. Treat the 8-Gbps statement as SK hynix’s characterization rather than as a fully verified standard limit.
For the same reason, supplier data should remain attributed. Samsung’s “up to 3,300 GB/s” and Micron’s “more than 2.8 TB/s” are valid descriptions of those companies’ stated products, not a single JEDEC-mandated HBM4 performance number.
Can consumers buy or upgrade to HBM4?
No standalone consumer HBM4 product has been identified in the official material covered here. HBM4 is supplied as part of an accelerator package or a complete HPC system. A standard desktop motherboard, generic graphics card, RAM kit or repair tool cannot be upgraded to HBM4 by swapping a module. Compatibility depends on the accelerator’s package, memory controller, power delivery, firmware and cooling design.
How HBM4 affects real model performance
When bandwidth is the constraint
If profiling shows that accelerator cores are frequently waiting for memory traffic, additional HBM bandwidth can raise useful throughput by feeding more data to those cores. The improvement still depends on whether software can issue enough parallel requests and use the available bandwidth efficiently.
When capacity is the constraint
If a model or batch does not fit in the available memory, adding bandwidth alone does not solve the problem. More capacity, a different stack configuration, quantization, sharding or a smaller batch may be required. A 36 GB stack and a planned or sampled 48 GB stack answer different capacity needs even when their bandwidth ratings are similar.
When compute or software is the constraint
If arithmetic throughput, communication between accelerators, kernel implementation or scheduling dominates runtime, HBM4’s interface may not be the limiting factor. Overall performance must therefore be measured on the complete accelerator and workload, not inferred from the memory specification alone.
Bottom line
HBM4 is stacked DRAM with TSVs, a base die and a 2,048-I/O interface designed to feed AI and HPC processors at very high throughput. Supplier material reports more than 2.8 TB/s per stack from Micron and up to 3.3 TB/s from Samsung, with capacities ranging from 24 GB to 36 GB in Samsung’s 12-layer products and 36 GB in Micron’s 12-high example. Those are implementation-specific figures. HBM4 matters because memory traffic can limit parallel AI computation, but the speed of a real model is determined by the entire accelerator, package, software and workload.
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