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Extreme ultraviolet (EUV) lithography is the chipmaking process that projects circuit patterns onto silicon with 13.5-nanometer light. Its much shorter wavelength than deep ultraviolet (DUV) lithography lets manufacturers print the most demanding layers of modern logic and memory chips with fewer pattern-splitting steps. That reduction in complexity is why EUV is central to 7 nm-, 5 nm-, and 3 nm-class production, and why the next generation of 0.55-NA High-NA EUV scanners is being developed for still denser designs.
What EUV lithography does
Photolithography transfers the geometry of a chip from a reticle onto a wafer coated with light-sensitive resist. The exposed resist is developed, and the resulting pattern guides etching, deposition or implantation. A modern chip repeats this sequence across many layers, so the scanner must align each new image with structures already on the wafer.
EUV changes the exposure light itself. Instead of the 193 nm wavelength used by high-resolution DUV systems, it uses 13.5 nm light. A shorter wavelength can resolve smaller pitches when paired with high-quality optics, accurate focus and tight process control. EUV is therefore used selectively on the layers whose dimensions and alignment tolerances are hardest to achieve.
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Process labels such as 3 nm or 2 nm are technology-generation names, not a promise that every printed line is exactly that wide. A node includes many dimensions, transistor structures, interconnect pitches, design rules and density targets. EUV supplies the patterning capability for critical layers within those generations; it does not manufacture a complete chip in one exposure or determine every dimension by itself.
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How an EUV scanner creates and projects the light
1. Making a laser-produced plasma
The source starts with molten tin droplets approximately 25 micrometers in diameter. The droplets travel through the source at roughly 70 meters per second. A lower-intensity laser pulse first flattens each droplet; a much stronger pulse then vaporizes it into plasma. The plasma emits EUV radiation, and this sequence can run up to 50,000 times per second.
This is a source-engineering problem as much as an optical one. The scanner must generate enough usable light for production while keeping debris, timing variation and contamination under control. ASML reported a 1,000-watt EUV light-source demonstration in April 2025 and described higher source power as a route to improved productivity. That demonstration is a source milestone, not a claim that every production tool operates at that power.
2. Guiding light through vacuum
EUV is absorbed by air and by ordinary optical materials. A conventional glass lens cannot transmit it, so the beam travels through a high-vacuum path and is shaped by multilayer mirrors. The mirrors use carefully engineered reflective coatings because each reflection loses some energy. Vacuum integrity, mirror cleanliness and thermal stability are essential to preserving image quality.
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The reticle is reflective rather than transparent. The projection optics reduce its pattern by a factor of four before it reaches the wafer. The scanner synchronizes reticle and wafer motion, controls focus and dose, and measures alignment against previously printed layers. The result is a controlled image transfer, not a simple photograph: exposure, resist behavior, etch bias and overlay errors all affect the final feature.
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Why EUV matters for advanced chips
Fewer multi-patterning operations
With DUV, a feature too small to print in one exposure can be divided across multiple masks and process passes. These multi-patterning schemes add deposition, exposure, etch, cleaning and metrology steps. Every additional pass consumes time and introduces opportunities for overlay error, defects and process variation.
EUV’s shorter wavelength allows more of the most complex layers to be printed with fewer patterning passes. It does not eliminate multi-patterning everywhere, but it can remove several splits from a critical layer. Fewer passes simplify process integration and can improve the practical economics of leading-edge production even when the scanner itself is extremely expensive.
More density at a given process generation
ASML says its 0.55-NA High-NA platform can print an 8 nm critical dimension. Compared with 0.33-NA NXE systems, the company specifies features 1.7 times smaller and transistor density 2.9 times higher. Those figures describe the lithography capability comparison supplied by ASML; actual chip density also depends on design rules, cell architecture, interconnect choices, process integration and yield.
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Current 0.33-NA NXE systems are used for critical layers in 7 nm-, 5 nm- and 3 nm-class logic and memory production. Memory manufacturers can use EUV where repeating structures become difficult to pattern economically with DUV. Logic manufacturers use it on layers that set transistor dimensions, contacts or dense wiring. The exact layer mix varies by product and process, so “EUV chip” does not mean every layer was exposed with EUV.
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DUV, 0.33-NA EUV and High-NA EUV compared
| Attribute | High-resolution DUV | 0.33-NA EUV (NXE) | 0.55-NA EUV (EXE High-NA) |
|---|---|---|---|
| Exposure wavelength | 193 nm | 13.5 nm | 13.5 nm |
| Numerical aperture | Not stated in the supplied technical material | 0.33 | 0.55 |
| Stated critical-dimension capability | Not stated | Not stated as one universal value | 8 nm |
| Primary role | High-resolution layers and support for multi-patterning | Critical layers in 7 nm-, 5 nm- and 3 nm-class logic and memory | Future leading-edge logic and memory production |
| Patterning implication | Often requires more multi-patterning for the smallest features | Reduces multi-patterning on selected complex layers | Targets still smaller features and higher density |
| Source power or throughput | Not stated | Current values vary by tool and disclosure | Current production values are not stated |
| System price | Not stated | About $150 million was reported for an EUV system in a 2023 U.S. government working-group report; this is dated context, not a current quote | Not stated |
Throughput, overlay accuracy, defectivity, energy per wafer and chemical consumption are important buying and process-engineering measures, but the cited material does not provide a single current value for each platform. They should be taken from the latest tool specifications and fab disclosures rather than inferred from wavelength or numerical aperture alone.
What High-NA EUV changes
Numerical aperture describes how much light an optical system can collect and how finely it can resolve detail. Moving from 0.33 to 0.55 NA increases the resolving capability of the EUV projection optics. ASML’s EXE platform is specified for an 8 nm critical dimension and is intended for future leading-edge logic and memory production.
Why higher NA is not a drop-in upgrade
Higher-NA scanners require new projection optics, reticle handling, wafer stages, focus control and computational correction. The optical field and exposure strategy can change, so chip designers and process engineers must account for stitching, layout restrictions and new process windows. A fab also has to qualify resists, masks, metrology and etch integration around the new tool.
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What the density claim means
The stated 1.7-times feature-size reduction and 2.9-times transistor-density increase are platform comparisons, not guaranteed gains for every circuit. Designers may trade density for speed, power, yield or routing flexibility. High-NA provides additional scaling headroom; it does not automatically deliver the same percentage improvement to a finished product.
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How EUV contributes to a 3 nm or 2 nm chip
- Design and mask preparation: Engineers create layouts that obey the node’s design rules, then fracture the layout into reticle data with optical and process corrections.
- Wafer preparation: A silicon wafer receives films and a light-sensitive resist. The wafer is aligned to marks from earlier layers.
- EUV exposure: The scanner forms EUV from tin plasma, reflects it through the vacuum mirror system, reduces the reticle image by four, and exposes selected fields.
- Development: The exposed resist is chemically developed to reveal the intended pattern.
- Pattern transfer: Etch or deposition transfers the resist image into the underlying film. Resist stripping and cleaning follow.
- Metrology and control: Critical dimensions, overlay and defects are measured. The results feed corrections for subsequent wafers and exposures.
- Layer repetition: The wafer cycles through many film, lithography, etch and measurement steps. DUV remains part of the flow for layers that do not require EUV.
- Device completion: Contacts, interconnects and other structures are built, followed by wafer test, dicing and packaging.
Thus, EUV is a key patterning stage inside a much larger manufacturing sequence. It enables dimensions and process simplification that would otherwise require more DUV patterning, but node performance still depends on materials, transistor architecture, process control, yield and design.
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Source, optics and contamination must work together
A usable scanner needs a stable EUV source, multilayer mirrors, a reflective reticle, vacuum chambers, fast wafer and reticle stages, sensors and control software. A weakness in any one subsystem can reduce dose stability, overlay performance or uptime. Tin debris and contamination are especially serious because a thin film on a mirror can reduce reflectivity.
Precision at production scale
Laboratory generation of EUV light is different from running a scanner continuously in a fab. Production tools must expose wafers repeatedly, maintain focus and alignment, manage heat and vibration, and provide predictable defect performance. The transition required coordinated advances in the source, optics, reticle, vacuum environment, wafer handling and software. ASML’s historical account describes collaboration with ZEISS and other research organizations during that transition.
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A 2023 U.S. government EUV working-group report recorded ASML with 100% market share for EUV systems at that time and described systems costing about $150 million. Both statements are dated context. They explain why ASML is central to EUV manufacturing history, but they should not be treated as a current market-share or purchase-price forecast.
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Limits and trade-offs
- Capital intensity: An EUV scanner is a major fab investment, with the cited $150 million figure applying to a 2023 report rather than a current quotation.
- Complex infrastructure: Vacuum equipment, source lasers, mirrors, stages, cooling, power and contamination controls all add facility requirements.
- Resist and stochastic variation: EUV photons arrive in relatively small numbers at the feature scale, so random variations in absorption and chemical response can affect defects and line-edge roughness.
- Mask complexity: Reflective masks require specialized multilayer construction and inspection, and mask defects can print onto many wafers.
- Not every layer benefits equally: DUV remains useful and may be more economical for larger or less critical features.
- Energy and chemicals: EUV can reduce some process steps, but the scanner and supporting infrastructure are energy-intensive. The net energy and chemical use per wafer depends on the complete process flow.
How to evaluate an EUV platform
Manufacturers and analysts should compare complete process capability rather than headline wavelength alone. The useful checklist is:
- Wavelength and numerical aperture
- Critical dimension and focus-exposure process window
- Overlay accuracy across layers and fields
- Source power, dose stability and wafer throughput
- Defectivity, mask inspection capability and contamination control
- Number of patterning steps removed or retained
- Logic or memory layers supported in the target process
- Energy, water and chemical use per wafer
- Tool availability, service model and integration with the fab’s metrology and etch systems
Published specifications are not interchangeable with guaranteed fab results. Ask which resist, mask, dose, field size, wafer size and process conditions produced a number, and whether it is a demonstrated capability, a target or a production qualification.
The bottom line on EUV’s importance
EUV is critical because it makes the smallest, most complex chip layers manufacturable with fewer patterning splits than a DUV-only approach. Its 13.5 nm light, reflective optics and vacuum architecture solve a problem that ordinary lenses cannot. The technology supports today’s leading-edge logic and memory production, while High-NA EUV extends the same approach toward smaller critical dimensions and higher density.
It is not a magic “3 nm printer.” EUV works inside a carefully controlled chain of masks, resists, etch, deposition, metrology, software and yield management. The fabs that gain the most from it are those that integrate the scanner with every one of those surrounding processes.
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