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Extreme ultraviolet (EUV) lithography projects circuit patterns onto silicon wafers with 13.5-nanometer light. Chipmakers use it mainly for the most intricate layers of leading-edge logic and memory devices, where the short wavelength can print features that would otherwise require more complicated deep-ultraviolet (DUV) multiple-patterning steps.
EUV is not a replacement for every other lithography method. A modern fab combines EUV, DUV and mature processes because each chip contains layers with different patterning requirements, and most chips do not need the smallest features.
What EUV lithography means
EUV stands for extreme ultraviolet. In semiconductor manufacturing, the term usually refers to scanners that use light with a 13.5 nm wavelength to transfer a mask pattern onto a photoresist-coated wafer. The scanner projects the pattern onto one layer of each die, the resist is developed, and subsequent etching or deposition steps turn that temporary image into part of the device structure.
The wavelength is the key distinction. EUV light is more than 14 times shorter than the 193 nm light used by common DUV immersion systems. Shorter wavelength gives the optical system a better starting point for resolving closely spaced lines and spaces. Resolution still depends on numerical aperture, illumination, resist behavior, process control and other factors; wavelength alone does not specify a transistor’s dimensions or a chip’s marketing node.
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What the number 13.5 nm does—and does not—tell you
- It is the illumination wavelength: the light used to expose the resist is centered at 13.5 nm.
- It is not a transistor measurement: a transistor gate, metal pitch or contact may be larger or smaller than 13.5 nm, depending on the process.
- It is not a node name: labels such as 5 nm or 3 nm describe a process generation, not a direct EUV wavelength or a single physical feature.
How an EUV scanner creates and focuses the image
An EUV tool has to generate, collect and control light that ordinary optical equipment cannot handle. The complete path is kept in high vacuum because air absorbs EUV radiation, as do most conventional optical materials.
- Droplet generation: a source fires a stream of tiny molten-tin droplets through a vacuum chamber.
- Laser-produced plasma: high-power laser pulses strike the moving droplets. The tin is converted into a hot plasma that emits EUV radiation around 13.5 nm.
- Collection: specialized collector optics gather the useful EUV photons while the source manages debris and heat from the plasma process.
- Mirror-based illumination: because EUV is absorbed by ordinary lenses and glass, the beam travels through multilayer reflective mirrors rather than refractive lenses.
- Reticle reflection: the patterned mask, called a reticle, is also reflective. The illumination reflects from its multilayer surface, carrying the circuit pattern.
- Four-times reduction: projection optics reduce the reticle image by a factor of four before it reaches the wafer.
- Wafer exposure: the scanner steps and scans across the wafer, exposing the selected layer in each die field. The wafer then moves to coating, baking, development, etch and deposition operations.
Every mirror surface and alignment system matters because even tiny losses reduce the number of photons available to expose the resist. Vacuum integrity, contamination control, thermal stability and nanometer-scale stage positioning are therefore part of lithography performance, not optional accessories.
Why chipmakers need EUV
Printing the most demanding layers
Leading-edge logic and memory chips contain many layers of wiring, contacts, gates and other structures. Only some layers have the tightest pitches. EUV is deployed on those intricate layers where its wavelength and optical design can resolve the pattern with fewer workarounds. Less demanding layers can continue to use DUV or mature lithography.
Reducing some multiple-patterning steps
With DUV, a pattern too dense for one exposure can be split across two or more masks and exposures. The wafer may need additional spacer, etch, alignment and inspection steps before the complete pattern is assembled. EUV can print certain dense patterns in fewer exposures, reducing some of that process complexity. The saving is not automatic: fabs still weigh scanner productivity, resist and mask costs, overlay control, defect rates, etch integration and yield.
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Keeping overlay under control
Every additional patterning pass creates another opportunity for alignment error between layers. Using EUV for an appropriate critical layer can reduce the number of alignments that would otherwise be required for a DUV multiple-patterning scheme. It does not eliminate overlay challenges; the EUV layer still has to align with neighboring layers and with the rest of the process.
Enabling economically viable scaling
The value proposition is system-level. A fab may accept a very expensive EUV scanner if its throughput, uptime, defect performance and reduced process count improve the cost per good die at an advanced node. Conversely, a chip with relaxed feature sizes may be cheaper and more reliable to manufacture entirely with DUV or mature tools. There is no universal rule that EUV lowers the cost of every chip.
EUV and DUV work together
DUV remains essential because a chip is not one repeating feature size. Large pads, peripheral circuits, less-dense metal layers and many mature products do not benefit enough from EUV to justify using it. A typical advanced process assigns EUV to selected critical layers and uses DUV for the rest.
| Characteristic | EUV | DUV |
|---|---|---|
| Typical exposure wavelength | 13.5 nm | Common advanced DUV systems use 193 nm; other DUV wavelengths and tools serve additional applications |
| Optical path | High vacuum with multilayer mirrors; ordinary lenses cannot transmit the light | Uses transmissive optical elements in a gas environment suitable for the wavelength |
| Patterning role | Selected, most intricate layers of leading-edge logic and memory | Many layers in advanced chips, plus mature and specialty devices |
| Multiple-patterning pressure | Can reduce some repeated exposures for dense layers | May require multiple exposures and extra process steps for patterns beyond one exposure’s capability |
| Availability and maturity | Highly specialized systems with demanding source and vacuum requirements | Broad, established manufacturing base across many nodes and products |
The practical question for a process engineer is not “EUV or DUV for the whole chip?” but “Which layers justify EUV, and which are better printed with DUV?”
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NXE and High-NA EXE: what changes between generations
Numerical aperture (NA) describes how much angular information the projection optics collect from the mask. A higher NA can improve resolution, but it also affects depth of focus, reticle strategy, field size, resist process and tool integration. The following figures are stated system specifications, not transistor dimensions or node definitions.
| Platform | Numerical aperture | Stated resolution | Positioning |
|---|---|---|---|
| NXE EUV systems | 0.33 NA | 13 nm | Current EUV platform used for selected critical layers in leading-edge production |
| EXE High-NA EUV systems | 0.55 NA | 8 nm | High-NA platform positioned for future advanced logic and memory manufacturing; rollout timing is a vendor roadmap statement |
Moving from 0.33 to 0.55 NA is not simply turning up a resolution dial. Fabs must qualify new optics, masks, resists, computational lithography, stage behavior and process windows. A published 8 nm resolution specification therefore should not be read as “8 nm transistors” or as proof that every layer of a future chip will use High-NA EUV.
What makes EUV difficult to operate
Low usable photon output
The plasma source produces EUV inefficiently. Much of the laser energy does not become usable light at the wafer, and collector mirrors lose part of what is generated. Photon scarcity can increase stochastic resist variation, such as random line-edge or line-width errors, particularly as features shrink.
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Tin plasma can produce debris and particles that threaten collector and projection mirrors. Protective systems, cleaning strategies and strict vacuum management are needed to preserve reflectivity. Mirror contamination directly affects dose, uptime and operating cost.
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Resist and mask limitations
The resist must absorb enough EUV to form a clean image while limiting roughness and defects. The reflective mask must have extremely accurate multilayer structures and absorber patterns. Any mask defect can print across many dies, so inspection and defect management are critical.
Throughput, uptime and yield
A scanner’s economic value depends on wafers per hour over sustained production, not on a laboratory image alone. Source power, maintenance intervals, stage speed, dose, overlay, defectivity and the percentage of good dies all contribute. A tool that resolves a pattern but cannot run consistently at the required throughput will not meet a high-volume fab’s needs.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Source-power milestones and what they mean
ASML reported a 1,000-watt EUV light-source demonstration in April 2025. That is a vendor-reported demonstration milestone, not a statement that every production scanner operates at 1,000 watts. Higher source power can support productivity goals, but the usable result still depends on conversion efficiency, mirror transmission, resist dose, uptime and defect control.
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ASML’s 2025 annual-report strategy material quotes Jayson Stewart, Head of Source Research: “For a long time, the output wasn’t powerful enough to make EUV a viable investment for customers.” The remark describes why source development and production economics are inseparable from the optical achievement.
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Where EUV fits in a chip fab
EUV exposure is one operation in a much longer pattern-transfer sequence. A simplified layer cycle looks like this:
- The wafer receives a film by deposition or grows an oxide or other material.
- A spin-coater applies photoresist, followed by soft-bake steps that set its thickness and chemistry.
- The EUV scanner aligns the wafer and exposes the reticle image field by field.
- Post-exposure bake and developer reveal the resist pattern.
- Etch transfers the pattern into the underlying film, or the resist opening guides deposition and lift-off.
- Cleaning, inspection and metrology check critical dimensions, overlay and defects before the next layer.
Because the process repeats across many layers, a small improvement on one critical layer can matter only if it integrates with the rest of the flow. EUV does not replace etch, deposition, metrology, packaging or design rules.
Common misunderstandings
“Every advanced chip is made entirely with EUV.”
No. EUV is normally reserved for selected intricate layers. DUV and mature tools print the remaining layers, and many chips do not need EUV at all.
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No. It identifies the exposure wavelength. Published resolution, transistor dimensions, metal pitch and process-node labels are different quantities.
“High-NA automatically means a new node.”
No. High-NA describes the optical numerical aperture. The 0.55 NA and 8 nm figures are system specifications; adopting them requires a complete process integration and manufacturing qualification.
“More EUV power always makes chips cheaper.”
No. Power can improve productivity potential, but total cost also includes tool utilization, masks, resist, maintenance, defects, process steps and yield. The economic outcome is specific to a fab and product.
Who actually needs EUV?
- Leading-edge logic manufacturers: companies producing the densest current or next-generation logic may use EUV on critical front-end and interconnect layers.
- Advanced memory manufacturers: dense memory arrays can benefit where pattern pitch and process complexity justify EUV.
- Mature-node and specialty manufacturers: many can meet their design rules with DUV or older lithography and have no economic reason to install EUV.
- Chip designers: designers do not “buy EUV” directly, but their target pitches, layer stack and design rules influence whether a foundry’s process uses it.
The bottom line for understanding EUV
EUV lithography is a 13.5 nm, mirror-based, vacuum lithography technology whose tin-droplet plasma source enables finer patterning than longer-wavelength exposure. Chipmakers need it selectively because the densest layers of leading-edge chips can become impractical to print with DUV multiple patterning alone. Its success depends as much on source power, uptime, masks, resist, overlay, defect control and yield as on optical resolution. EUV therefore complements rather than replaces DUV, and the majority of chips still do not require it.
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