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An AI inference accelerator is specialized hardware that runs a trained model to produce predictions or generated output. FP8 (8-bit floating point) can make matrix calculations faster and reduce data movement, but an advertised FP8 number is a theoretical ceiling for a particular operation—not an application’s tokens-per-second result. Real inference depends on whether the model, activations and key-value (KV) cache fit in memory; how quickly memory supplies them; batch size and concurrency; input and output lengths; software support; interconnects; power limits; and the latency target.
For a useful decision, compare measured results for the same model, precision, sequence lengths, concurrency, accelerator count and software stack. Read compute, memory capacity and bandwidth together instead of ranking hardware by peak FP8 figures alone.
What an AI inference accelerator does
Inference is the execution phase after training. A service loads trained weights, accepts an input such as a prompt or image, and calculates a prediction or generated response. An inference accelerator is a processor designed to execute the matrix and tensor operations in those models efficiently. It typically combines specialized matrix or tensor engines with high-bandwidth memory and software libraries that map model operations to the hardware.
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For large-language-model (LLM) services, useful measurements include tokens per second, time to first token and inter-token latency. A batch job that maximizes aggregate throughput has a different objective from an interactive assistant that must begin responding quickly. The same accelerator can therefore look fast or slow depending on the service target.
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Current examples illustrate the range of designs. NVIDIA documents FP8 support in the H100 Tensor Cores (H100 specifications), while AMD documents FP8 capability for the MI300 series (AMD Instinct MI300 series). Those capabilities indicate what the hardware can execute; they do not promise a particular model’s end-to-end speed.
What FP8 performance actually tells you
FP8 is a data format and operating mode
FP8 represents values with 8 bits. Using fewer bits can reduce the amount of data moved and allow dedicated matrix units to process more values per cycle. Inference software may apply FP8 to weights, activations, or selected operations, with scaling and calibration needed to preserve numerical behavior. A model cannot be assumed to retain identical quality after conversion: the acceptable precision and quantization method depend on the model and implementation.
Peak FP8 is a ceiling, not a serving result
A specification such as “FP8 TFLOPS” describes the maximum rate for a defined operation under ideal hardware conditions. A real service also spends time loading weights, reading and writing activations and KV-cache entries, coordinating devices, scheduling requests and running kernels that may not use the FP8 path. Small batches, irregular tensor shapes or unsupported operators can leave matrix units underused.
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteAMD labels the MI300X FP8 figure as peak theoretical performance. Its product page lists 2,614.9 TFLOPS, calculated by AMD Performance Labs on November 11, 2023 (AMD specifications). The page also presents a sparsity figure; a sparse result must not be compared with a dense number as if they measured the same work.
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Measured workload data looks different. Intel’s Gaudi 3 table reports tokens per second for named models, sequence lengths, batch sizes, accelerator counts and software versions (Intel Gaudi 3 performance data). Those numbers are useful only with their test conditions attached.
Why memory capacity can decide whether a model runs
Accelerator memory must hold model weights, temporary activations and inference state. For an LLM, the KV cache grows as prompts and generated conversations become longer and as concurrent requests increase. Capacity therefore affects more than whether the weights fit: it can determine the maximum context length, batch size or concurrency that fits without spilling data or adding another device.
A simple capacity estimate
As a first estimate, multiply the number of parameters by the bytes used for each stored weight. FP8 uses roughly one byte per value, so 70 billion parameters represent roughly 70 GB of raw weight data before scales, metadata, runtime buffers and KV cache. This is an illustration, not a deployment requirement: real frameworks reserve additional memory, and the cache size depends on architecture, context length, precision and active requests.
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What the named benchmark observations show
NVIDIA says the H200’s larger memory allowed its tested Llama 2 70B MLPerf workload to avoid tensor or pipeline parallel execution, reducing communication overhead. This is an observation about that benchmark configuration, not a universal rule for every 70B model or serving engine (NVIDIA’s MLPerf discussion).
A Signal65 analysis in an Intel/IBM Cloud white paper reports different behavior in Llama 3.1 405B tests. The tests used eight available cards per environment and examined 1,024/1,024- and 4,096-token input configurations. At some larger batches, the paper says H100 was constrained by KV-cache memory, while Gaudi 3 throughput differed relative to H100 and H200. The exact card count, context lengths and batch settings are essential when interpreting that comparison (Signal65 and Intel/IBM Cloud white paper).
When memory bandwidth limits inference
Memory bandwidth is the rate at which weights, activations and cache data can move between memory and compute units. Autoregressive decoding often rereads substantial weight and cache data for each generated token. If those reads take longer than the arithmetic, the workload is memory-bound and additional compute units provide little benefit.
NVIDIA attributes part of the H200 Llama 2 70B improvement in its MLPerf discussion to higher memory bandwidth relieving bottlenecks and allowing greater Tensor Core utilization (NVIDIA’s MLPerf discussion). Bandwidth does not guarantee an end-to-end gain: a workload can instead be limited by compute, communication, kernel availability, scheduling or host-side processing.
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Capacity and bandwidth are separate constraints. A device can have enough memory to hold a model but move data too slowly for the target latency, or offer very high bandwidth while lacking capacity for the desired context and concurrency.
Named specifications and results in context
The following figures come from different sources and measurement types. They are not an apples-to-apples ranking.
| Accelerator or result | Memory and bandwidth | FP8 or workload figure | How to interpret it |
|---|---|---|---|
| NVIDIA H200 | 141 GB HBM3e; 4.8 TB/s. NVIDIA marks these product specifications as preliminary and says capacity is nearly twice H100’s with 1.4 times H100’s bandwidth. | NVIDIA reports up to 28% better Llama 2 70B inference at an equal stated 700 W TDP, and up to 45% at a 1,000 W H200 TDP. | Vendor descriptions of specific MLPerf Inference v4.0 submissions; not a general guarantee. The product page and blog use particular configurations and, in some comparisons, different batch sizes (H200 product page). |
| AMD Instinct MI300X | 192 GB HBM3; 5.325 TB/s. AMD dates the memory calculation to November 17, 2023. | 2,614.9 TFLOPS peak theoretical FP8, calculated November 11, 2023. | A vendor theoretical ceiling, not tokens per second. Do not compare directly with a benchmark throughput number (AMD specifications). |
| Intel Gaudi 3, Llama 3.1 70B example | Two HPUs in the cited test. | 128 input tokens, 128 output tokens, batch size 2,048: 5,466 tokens/sec. | Measured table result using software 1.20 unless otherwise noted and PyTorch 2.6.0. Its high batch and short sequences describe an offline-style configuration, not every online service. |
| Intel Gaudi 3, another Llama 3.1 70B example | Two HPUs in the cited test. | 2,048 input tokens, 128 output tokens, batch size 223: 663 tokens/sec. | Not directly comparable with the previous row because input length and batch size differ. Both figures are from Intel’s performance table (Intel Gaudi 3 performance data). |
These examples demonstrate why a large FP8 number cannot be converted into a universal tokens-per-second expectation. The MI300X figure is theoretical; the H200 figures are vendor-reported benchmark comparisons; and the Gaudi 3 values are measured under explicit model and batch settings.
How to evaluate an accelerator for your workload
- Describe the production request. Record the model revision, expected prompt or input-length distribution, generated output length, peak concurrent requests and whether the service is interactive or batch-oriented.
- Choose the numerical path. Specify FP8, FP16, BF16 or another format, and state whether FP8 applies to weights, activations or both. Validate quality on representative prompts before treating a faster format as acceptable.
- Check the working set. Estimate weight storage, then add runtime buffers, activations and KV cache for the longest context and planned concurrency. Confirm the framework’s usable memory rather than relying only on the headline capacity.
- Decide the device layout. Test whether one accelerator can hold the working set. If partitioning is required, record tensor or pipeline parallelism, the number of devices and the interconnect, because synchronization can consume a significant share of time.
- Use a production-like software stack. Record the framework, compiler, serving engine, kernels, driver and versions. Verify that the model’s operators have optimized FP8 implementations; unsupported operations can force slower paths.
- Measure both throughput and latency. Report tokens per second alongside time to first token and inter-token latency. Test several batch sizes or request-concurrency levels rather than selecting the one that produces the largest number.
- Apply the same test to each candidate. Keep model revision, precision, input and output lengths, concurrency, accelerator count, power limit and software versions constant. Publish the complete configuration with every result.
- Calculate service economics. For a matched service target, include accelerator count, power, host and networking requirements, utilization and current acquisition or rental cost. A throughput result without a cost and power boundary cannot establish total cost of ownership.
Common interpretation mistakes
Treating peak FP8 as end-to-end speed
Peak arithmetic assumes favorable operations and utilization. Replace it with measured tests that include loading, cache traffic, communication and all model operators.
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Comparing unlike benchmark rows
Changing prompt length from 128 to 2,048 tokens or changing batch size changes the work and memory behavior. The two Gaudi 3 examples above illustrate why a larger tokens-per-second number does not automatically indicate a faster device.
Ignoring KV-cache growth
A model may load successfully and then fail at the intended concurrency because each additional request extends the cache. Test the longest realistic context and peak simultaneous sessions.
Assuming bandwidth alone solves the bottleneck
Bandwidth helps when memory movement is limiting, but compute saturation, interconnect traffic, software kernels and latency constraints can dominate instead.
Mixing vendor claims with independent results
Label product specifications, vendor benchmark submissions and third-party tests separately. NVIDIA’s “up to” figures are vendor descriptions of particular MLPerf configurations; they are not an independent guarantee for an arbitrary deployment.
A practical decision framework
- Choose capacity first when the model, cache and required concurrency do not fit on one device. Reducing device count can remove communication overhead, but only if the working set genuinely fits.
- Prioritize bandwidth when profiling shows repeated weight or cache reads dominate token latency and the software already keeps compute units supplied.
- Prioritize compute when large, well-shaped batches keep matrix units busy and arithmetic, rather than memory traffic, is the measured bottleneck.
- Prioritize software maturity when your model uses uncommon operators, custom quantization or a serving engine with limited FP8 kernels. A nominally powerful accelerator can underperform if the execution path falls back to generic code.
- Prioritize latency and interconnect for interactive services or partitioned models. Aggregate throughput alone can hide slow first-token response or synchronization delays.
There is no universal winner established by the cited figures. The appropriate accelerator is the one that meets your model’s quality, capacity, latency and concurrency requirements at acceptable power and cost under a reproducible test.
Bottom line
FP8 can raise mathematical throughput, but it is only one part of inference performance. Memory capacity determines whether the model and its runtime state fit; bandwidth determines how quickly that state can feed the compute units; and workload shape, software, interconnect, power and latency targets determine how much of the hardware’s potential becomes useful application throughput. Benchmark the exact workload under matched conditions, and publish the configuration with the result.
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