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Micron makes semiconductor memory and storage based mainly on DRAM, NAND flash, and NOR technologies. In an AI data center, those technologies occupy different layers: high-bandwidth memory (HBM) sits next to an accelerator, DDR5 or low-power modular memory supplies the server’s working memory, and NAND-based data-center SSDs retain models, datasets, and caches when power is removed. The products are complementary, not interchangeable, and Micron is a broad memory manufacturer rather than an AI-only company.
What Micron manufactures
Micron’s 2025 Form 10-K describes a portfolio built on three memory technologies. The distinction matters because each technology has different speed, persistence, capacity, and system-design characteristics.
DRAM: volatile working memory
Dynamic random-access memory (DRAM) holds data temporarily while a processor works on it. It is volatile: removing power causes its contents to disappear. DRAM is used in data-center servers, client computers, graphics systems, industrial equipment, mobile devices, and vehicles. HBM, DDR5 modules, and LPDDR-based modular products are all specialized forms of DRAM aimed at different physical locations and power or bandwidth targets.
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NAND flash: persistent storage
NAND flash retains data without power. Micron uses it in solid-state drives and in managed NAND products that combine flash with a controller and firmware. NAND is slower to access than the closest DRAM, but it provides the persistence and high capacity required for operating systems, training datasets, model files, logs, and large caches.
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NOR: code-oriented non-volatile memory
NOR flash is another non-volatile technology in Micron’s portfolio. It is commonly suited to firmware and embedded code storage rather than the bulk storage role of a data-center SSD. Its presence in the portfolio illustrates that Micron serves embedded and automotive markets as well as hyperscale computing.
Different commercial forms
Micron sells memory as individual components, modules, SSDs, managed NAND, multichip packages, and wafers. A system-level product can combine NAND, a controller, firmware, and sometimes DRAM. A wafer is an intermediate manufacturing form; a server operator normally buys a qualified module or drive rather than installing a bare wafer.
Why AI data centers use a memory hierarchy
AI workloads repeatedly move model weights, activations, attention data, and intermediate results between compute engines and storage. A single memory type cannot optimize all of those transfers. Designers therefore build a hierarchy:
- Accelerator-local memory: HBM provides very high bandwidth beside a GPU, AI accelerator, or other compute device.
- Host or system memory: DDR5 modules and LPDDR-based SOCAMM modules provide larger working memory around CPUs and other platform components.
- Persistent storage: NAND-based SSDs keep data available across reboots and provide capacity beyond DRAM.
Moving a frequently used tensor or key-value (KV) cache into a faster tier can improve throughput, but capacity, power, latency, interconnects, cooling, and platform qualification determine whether that move is practical. Micron’s June 2026 positioning describes HBM for high-speed model execution and hot KV cache, LPDDR and DDR for system memory, and SSDs for persistent KV cache and high-capacity storage. Those are Micron’s product-positioning statements, not a universal architecture requirement.
HBM: memory next to the AI accelerator
What HBM does
High-bandwidth memory is built from stacked DRAM dies connected through a very wide interface. Packages place the stacks close to the accelerator, shortening the path data travels and allowing many bits to move in parallel. During training, HBM feeds weights and activations to matrix engines; during inference, it supplies model parameters and attention data at the rate the accelerator can consume them.
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Published HBM4 specifications
Micron’s HBM4 product page lists a 2,048-pin bus interface operating above 11.0 Gb/s and bandwidth above 2.8 TB/s per stack. These are vendor-published specifications, not independent benchmark results. Actual application performance also depends on the accelerator, number of stacks, software, workload shape, and the rest of the memory system.
Capacity and placement trade-offs
HBM offers exceptional bandwidth, but its capacity is limited by package space and stack configuration. Increasing HBM can reduce transfers to slower tiers, while adding host memory or SSD capacity can be less expensive for data that is not on the critical path. HBM cannot simply replace server DIMMs or SSDs: it uses a different package and interface and must be supported by the accelerator platform.
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Dated HBM4 production status
In a March 16, 2026 announcement, Micron said its HBM4 36GB 12-high product was in high-volume production and designed for NVIDIA Vera Rubin. Production status and platform pairing are time-sensitive statements from Micron and can change as qualification and customer roadmaps change.
DDR5, RDIMMs, and MRDIMMs: the server’s working memory
Why host memory is still needed
CPUs orchestrate data loading, preprocessing, networking, storage I/O, and many control tasks around an accelerator. They need substantial addressable memory even when the model’s hottest tensors reside in HBM. DDR5 server modules provide that general-purpose working space for operating systems, databases, data pipelines, and memory-intensive AI or high-performance-computing workloads.
RDIMM and MRDIMM choices
Registered DIMMs (RDIMMs) buffer control signals so servers can support larger capacities and more reliable multi-module configurations than ordinary unbuffered desktop memory. Multiplexed-rank DIMMs (MRDIMMs) are another server-oriented design intended to increase effective bandwidth through module-level data handling. The right choice is constrained by the CPU generation, motherboard, firmware, maximum supported capacity, channel population rules, and workload. A DIMM that fits physically is not automatically electrically or firmware-compatible.
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DDR5 is not HBM
DDR5 sits on the server’s memory channels and is optimized for scalable system capacity and general access. HBM is packaged beside the accelerator and optimized for extreme bandwidth over a very wide interface. A server may use both: HBM for accelerator-local traffic and DDR5 for host operations, staging, and data that does not fit in HBM.
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Micron positions LPDDR5X-based SOCAMM and SOCAMM2 as modular memory for AI-data-center and HPC platforms. LPDDR technology emphasizes lower power per transferred bit, while a replaceable module preserves more serviceability and capacity flexibility than memory soldered directly to a system board.
This design is a trade-off, not a universal replacement for DDR5 or HBM. Platform designers must balance capacity, bandwidth, power, thermal limits, module placement, and processor support. In its March 16, 2026 announcement, Micron reported SOCAMM2 high-volume production, including a 192GB module, and a stated product range from 48GB to 256GB. Those capacities and production claims are tied to that announcement date.
Data-center SSDs: persistent capacity and cache
Micron’s data-center SSDs use NAND flash with a controller and firmware to provide non-volatile block storage. They hold training corpora, checkpoints, model repositories, container images, telemetry, and the operating system. Unlike DRAM, they retain information through a power cycle.
Persistent KV cache
Large-language-model serving can build a KV cache containing attention state for active conversations. Keeping a hot portion in HBM or system DRAM minimizes latency; moving colder portions to a high-performance SSD can extend context or reduce the amount of expensive DRAM required. The result is a tiered cache, not a claim that an SSD has DRAM-like latency.
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Capacity-oriented data lakes
High-capacity SSDs store datasets and checkpoints close to compute nodes, reducing dependence on remote storage for every read. The benefit depends on the file system, network, replication policy, queue depth, and access pattern.
9650 PCIe Gen6 status
Micron’s March 16, 2026 announcement said its 9650 PCIe Gen6 data-center SSD was in high-volume production. That is a dated vendor status, not an independent endurance, latency, or throughput test.
How the tiers work together in an AI job
- Load and prepare data: datasets and model files reside on persistent SSD or a connected storage system. CPUs use host memory while decompressing, tokenizing, and shuffling data.
- Stage tensors: the runtime transfers frequently needed weights and batches from system memory toward the accelerator. The interconnect and software schedule these transfers to avoid starving compute.
- Execute in HBM: accelerator engines read weights, activations, and attention state from HBM at very high bandwidth. Capacity pressure may require partitioning or movement to another tier.
- Manage overflow and sharing: less-active state can remain in DDR5, SOCAMM2, or an SSD-backed cache. The farther data is from the accelerator, the greater the likely latency and software-management cost.
- Persist results: checkpoints, fine-tuned weights, logs, and generated outputs are written back to SSD or another durable storage layer.
This workflow explains why “memory for AI” is not a single product category. Performance is governed by the slowest or most congested path that matters to the specific workload.
Product-family comparison
| Product family | Physical/system location | Primary role | Persistence | Key design concern |
|---|---|---|---|---|
| HBM, including HBM3E and HBM4 | Packaged beside an accelerator | High-bandwidth model execution and hot data such as KV cache | Volatile | Accelerator compatibility, stack capacity, package and thermal limits |
| DDR5 RDIMM/MRDIMM | CPU memory channels | General server working memory and AI/HPC staging | Volatile | Platform qualification, channel population, capacity and reliability |
| LPDDR5X SOCAMM/SOCAMM2 | Modular system-memory position | Lower-power host memory for supported AI and HPC platforms | Volatile | Processor and module support, power, capacity and serviceability |
| Data-center SSD | PCIe/NVMe storage subsystem | Persistent models, datasets, checkpoints and cache tiers | Non-volatile | Latency, endurance, capacity, queueing and storage software |
No single row is a universal “best” choice. HBM targets bandwidth, host modules target working-set capacity and system flexibility, and SSDs target persistence and scale.
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Micron’s June 1, 2026 COMPUTEX announcement said its HBM4 36GB 12-high product enabled a 2.6-times increase in LLM inference throughput for every two-times increase in bandwidth, according to Micron’s stated measurement. The announcement’s measurement framing and test conditions should be treated as part of the claim; it is not an independently reproduced benchmark.
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“AI context lengths are increasing by 30 times per year, while memory content per server has doubled in the past three years,” said Sumit Sadana, Micron’s executive vice president and chief business officer, on June 1, 2026.
That sentence is Micron’s executive statement, not an independent industry statistic. More generally, Micron’s production dates, product pairings, bandwidth figures, and demand statements should be read with their publication dates and attribution because roadmaps and qualifications evolve.
How to match memory to a data-center workload
For accelerator-bound training
Start with the accelerator’s supported HBM generation, stack count, capacity, and thermal envelope. If the model or batch does not fit, evaluate partitioning, host-memory staging, or model changes rather than assuming that adding an unrelated DIMM will solve an HBM-capacity limit.
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For large inference fleets
Measure model size, concurrent sessions, context length, KV-cache growth, and target latency. HBM serves the hottest execution path; DDR5 or SOCAMM can hold broader working sets; SSDs can provide a persistence or colder-cache tier when the software stack supports it.
For data preparation and analytics
Prioritize host-memory capacity, memory-channel balance, storage throughput, and network behavior. These jobs may gain more from balanced DDR5 and fast SSDs than from additional accelerator-local HBM.
For platform procurement
Use the server and accelerator manufacturer’s qualified-memory list. Verify module type, rank, capacity per slot, firmware requirements, PCIe generation, endurance rating, service procedures, and support dates. Capacity numbers quoted for one product family cannot be transferred to another without checking the platform.
Common misconceptions and failure modes
- “All memory is interchangeable.” HBM, DDR5, SOCAMM2, and SSDs use different interfaces, locations, and persistence models.
- “More bandwidth always makes the application faster.” An application limited by compute, networking, synchronization, storage latency, or insufficient capacity may see little benefit.
- “An SSD is just slower RAM.” It is a persistent storage device with different latency, endurance, queueing, and software semantics.
- “A published peak is an application benchmark.” Micron’s above-2.8-TB/s-per-stack HBM4 figure is a vendor specification; the stated inference-throughput result is a company measurement with its own framing.
- “A production announcement guarantees availability everywhere.” High-volume production on a stated date does not establish regional inventory, a customer’s qualification, or future roadmap continuity.
Bottom line
Micron’s DRAM, NAND, and NOR technologies appear in multiple products because AI data centers need multiple memory tiers. HBM4 and other HBM products feed accelerators at extreme bandwidth; DDR5 modules and SOCAMM2 provide volatile server working memory; and data-center SSDs preserve models, datasets, checkpoints, and colder cache data. Choosing among them requires a specific platform and workload, with every capacity, bandwidth, and production claim checked against its date and source.
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