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Data centres need a coordinated semiconductor system, not just AI accelerators. CPUs, several kinds of memory, persistent storage, networking and interconnect silicon, optical components, and power-management devices determine whether an accelerator can be fed with data, connected to other servers, supplied with stable power, and operated reliably. The right mix depends on the workload and the architecture: an AI training cluster prioritises accelerator memory bandwidth and scale-out links, while general cloud, database, and storage services also require substantial CPU capacity, conventional DRAM, SSDs, and network connectivity.
The semiconductor stack behind a data centre
An accelerator is only one processing element in a much larger system. A production data centre must move data from storage to memory, between CPUs and accelerators, across servers and racks, and sometimes between geographically separate sites. It must also convert incoming electrical power into tightly controlled voltages, monitor temperatures and faults, and keep systems serviceable for years.
The most useful way to assess semiconductor suppliers is therefore by the job each component performs and by how well the parts work together. A fast device that cannot be qualified with the target platform, supplied in volume, cooled within the rack design, or supported through its intended service life is not a practical data-centre component.
CPUs for control and general-purpose work
Server CPUs run operating systems, virtual machines, databases, orchestration software, storage services, security functions, and the portions of an application that are not assigned to an accelerator. They coordinate data movement and system activity even in heavily accelerated environments. CPU selection affects memory capacity, I/O lanes, virtualization features, telemetry, and the number and type of accelerators that can be attached.
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For a mixed cloud fleet, CPU capacity may be the dominant requirement. In an AI training pod, the CPU still handles input pipelines, checkpointing, scheduling, and network and storage control. Suppliers must therefore provide platform compatibility, firmware support, predictable availability, and a roadmap that matches the server’s expected operating life rather than focusing only on peak benchmark performance.
HBM, server DRAM, and persistent storage are different
“Memory” is not one interchangeable category. High-bandwidth memory (HBM) sits close to an accelerator package and supplies very high data bandwidth for active model parameters and workloads that repeatedly stream data through compute units. Its value is bandwidth and proximity, not replacing all of the system’s capacity.
Server DRAM, including DDR5 registered DIMMs (RDIMMs), provides the larger volatile address space used by CPUs, operating systems, databases, virtual machines, and application buffers. It generally offers more capacity per server than accelerator-attached HBM, but with a different bandwidth and latency profile. A server can need both types simultaneously.
NAND-based data-centre SSDs provide persistent storage. They retain operating systems, databases, datasets, logs, model checkpoints, and intermediate results when power is removed. SSDs are connected through interfaces such as NVMe over PCIe and are constrained by endurance, queue depth, latency consistency, capacity, and write amplification rather than by the same metrics used for HBM.
Micron’s September 2026 Form 10-K describes a data-centre portfolio spanning HBM, high-capacity DIMMs, low-power server DRAM, DDR5 RDIMMs, data-centre SSDs, and NAND products. That portfolio illustrates why a bill of materials should keep accelerator memory, system memory, and storage as separate line items.
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| Layer | Primary job | Typical decision criteria | Failure or mismatch risk |
|---|---|---|---|
| HBM | Feeds accelerators with very high local bandwidth | Bandwidth, capacity per package, thermal limits, package compatibility, supply | Accelerator is underfed or package cannot be qualified |
| DDR5/RDIMM server DRAM | Provides CPU-attached volatile system memory | Capacity, bandwidth, latency, ECC/RAS features, qualified module list | Insufficient address space, instability, or unsupported modules |
| NAND data-centre SSD | Stores data persistently | Capacity, endurance, QoS latency, throughput, power, controller and firmware support | Checkpoint delays, tail-latency spikes, or premature wear |
| CPU | Runs general-purpose code and coordinates the platform | Core and I/O capacity, virtualization, memory channels, power, lifecycle | Control-plane bottlenecks or poor accelerator utilisation |
Why data movement is a first-class design problem
Accelerator performance is useful only when data arrives on time. Silicon in switches, host interfaces, memory-expansion devices, storage controllers, and optical links determines how quickly information travels inside a server, between racks, and between sites.
Ethernet, PCIe, and switching silicon
PCIe connects CPUs to accelerators, SSDs, network adapters, and other peripherals inside a server. Ethernet and switching silicon carry traffic between servers and racks, including distributed training traffic, storage access, service-to-service calls, and management operations. Supplier evaluation should consider lane count, generation and link speed, switching capacity, buffering, congestion management, telemetry, and software support.
Marvell’s portfolio descriptions include Ethernet and PCIe switch silicon, storage connectivity, optical digital signal processors, and Compute Express Link (CXL) products. These are examples of the functions suppliers serve; they do not establish that one interface or topology is optimal for every operator.
CXL memory expansion and pooling
CXL can attach memory resources beyond the CPU’s directly attached DIMMs, allowing architectures that expand or pool capacity. The practical outcome depends on the CXL version, device type, operating-system and firmware support, NUMA behaviour, latency tolerance, and the software’s ability to place data intelligently. A pooled-memory design can improve utilisation, but it may add another latency tier that applications must understand.
Optical engines and silicon photonics
As links become faster and rack distances increase, copper reaches limits in loss, power, and reach. Optical engines, photonic integrated circuits, laser and modulator components, optical digital signal processors, high-speed electrical drivers, and control electronics convert data between electrical and optical domains. They support links within a large system, between racks, and potentially between buildings or sites.
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STMicroelectronics describes photonic integrated circuits, optical engines, high-speed electronics, and control components as part of the infrastructure around cloud AI. The design choice still depends on distance, lane speed, connector density, serviceability, thermal budget, and the operator’s network architecture. An optical component should be judged as part of the complete transceiver or link, not in isolation.
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Power semiconductors keep the platform usable
Every processor, memory device, switch, SSD, and optical module needs stable power at the voltage and current its circuits require. Power-management ICs, multiphase voltage regulators, controllers, clock generators, monitoring devices, and power transistors convert and regulate energy at the board and server levels. Gallium nitride (GaN) and silicon carbide (SiC) devices can be used in relevant conversion stages where their switching and efficiency characteristics fit the design.
Power silicon contributes to conversion efficiency, transient response, fault protection, current sharing, telemetry, and thermal management. Poor regulation can cause errors or resets even when the compute silicon is correctly specified. Suppliers should provide reference designs, control firmware, protection features, measurement accuracy, and long-term support for the chosen platform.
These semiconductor roles should not be confused with the wider facility infrastructure. Grid interconnection, backup generators, uninterruptible power systems, cooling plants, busways, and building construction are essential data-centre requirements, but they are not all semiconductor products. The chip supplier’s responsibility is the conversion, control, monitoring, and protection circuitry within the relevant electrical chain.
How priorities change by workload
There is no universal data-centre bill of materials. A training cluster, an inference service, a general-purpose cloud, and a storage platform stress different parts of the semiconductor stack.
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| Workload or deployment | Highest-priority semiconductor concerns | Important secondary concerns |
|---|---|---|
| Large-model training | HBM bandwidth and capacity, accelerator-to-accelerator scale-out links, high-radix switching, optical reach, power delivery | CPU input pipelines, DDR5 capacity, checkpoint SSD throughput, telemetry and fault isolation |
| Accelerated inference | Predictable accelerator latency, memory capacity, host-to-device connectivity, power per request | CPU scheduling, network fan-out, SSD model loading, serviceability |
| General cloud and virtualisation | CPU core and I/O capacity, DDR5/RDIMM capacity, Ethernet switching, reliability features | SSD endurance, CXL expansion, power efficiency, remote management |
| Databases and analytics | DRAM capacity and latency, CPU performance, SSD QoS and endurance, network throughput | Compression or encryption acceleration, CXL tiers, power and thermal headroom |
| Storage-heavy services | NAND SSD capacity, endurance, controller quality, PCIe connectivity, network bandwidth | CPU and DRAM for metadata and caching, power-loss protection, fleet telemetry |
The same facility may contain all of these profiles. Procurement should map components to each service class instead of applying a single rack ratio to the entire site.
What published rack percentages do—and do not—tell you
A May 2026 Semiconductor Industry Association and Deloitte analysis of a specified AI data-centre server rack estimated that memory and storage semiconductors represented more than 20% of the rack’s semiconductor content value. In the same report’s model, logic and memory together represented more than 85% of semiconductor value.
Those figures are useful for showing that memory and storage are material parts of an AI system, but they are not universal averages for every data centre. The result depends on the report’s rack definition, included components, prices, configuration, and accounting method. A conventional cloud rack, a storage appliance, and a next-generation training rack can have very different mixes.
Industry investment forecasts also need their date and status attached. SEMI’s June 29, 2026 release projected worldwide 300mm memory-fab equipment investment of $52 billion in 2026, a 29% annual increase, and $57 billion in 2027. These are forecasts, not realised spending. SEMI President and CEO Ajit Manocha said: “Strong demand for high bandwidth memory and other advanced memory technologies is reshaping investment priorities across the semiconductor supply chain,”. The statement explains the direction of investment but does not guarantee a particular supplier’s capacity or delivery date.
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Supplier comparisons should use the same workload, interfaces, qualification rules, and operating assumptions for every candidate. Product-page specifications alone cannot establish fleet suitability.
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- Workload fit: Test against training, inference, general cloud, storage, or mixed-use requirements, including peak and sustained behaviour.
- Compatibility and integration: Check platform support, interface generation, memory type, package and board constraints, firmware, drivers, operating-system support, and system qualification.
- Performance: Compare bandwidth, usable capacity, latency distribution, throughput, queue-depth behaviour, and scaling across multiple devices or racks.
- Efficiency and operations: Measure power per completed workload, thermal output, telemetry quality, reliability features, serviceability, and fault containment.
- Supply and lifecycle: Confirm qualification status, volume availability, roadmap, support period, change-notification policy, and credible second-source options.
The available public material supports these dimensions, but it does not provide a neutral head-to-head ranking, market-share table, or procurement-availability assessment. A buyer should obtain those facts through qualification and commercial due diligence.
A practical qualification workflow
- Define the service profile. Record model size, batch or transaction pattern, storage working set, network traffic, latency target, availability objective, and expected growth.
- Draw the data path. Identify where data resides, how it reaches CPU and accelerator memory, which links cross the rack boundary, and where optical conversion occurs.
- Set capacity and bandwidth separately. Specify HBM bandwidth, DDR5 capacity, SSD usable capacity and endurance, and network throughput as distinct requirements.
- Check electrical and thermal envelopes. Match regulator phases, transient response, device power, cooling capability, connector ratings, and telemetry to the server and rack design.
- Run representative tests. Measure sustained throughput, tail latency, error rates, recovery behaviour, and power under the actual software stack rather than relying only on peak data-sheet numbers.
- Complete platform qualification. Validate firmware, drivers, memory training, PCIe or Ethernet interoperability, CXL behaviour if used, secure boot, remote management, and replacement procedures.
- Review supply resilience. Examine lead times, manufacturing locations, allocation risk, end-of-life notices, engineering-change processes, and second-source compatibility.
- Approve the complete system. Select a component only after its interaction with processors, memory, storage, networking, optics, power, and cooling has been documented.
Where ECC DDR5 RDIMMs fit
ECC DDR5 RDIMMs are a practical example of a component that must be bought for a specific platform, not simply for a headline capacity. Before installing one, verify the server manufacturer’s qualified vendor list, supported DDR5 speed, rank and density limits, maximum DIMMs per channel, population rules, firmware level, and required error-correction mode. A module can be electrically similar yet unsupported because of density, timing, rank, or firmware constraints. The category is relevant to server upgrades, but a particular module, price, retailer listing, or compatible SKU is not established here.
Common mistakes and how to avoid them
- Treating HBM as all required memory: Keep accelerator bandwidth, CPU-attached DRAM capacity, and persistent SSD storage in separate specifications.
- Using one rack estimate as a universal budget: Recalculate the mix for each workload and rack design.
- Optimising compute while ignoring movement: Model PCIe, Ethernet, switching, CXL, storage, and optical bottlenecks before increasing accelerator count.
- Comparing peak numbers only: Include sustained throughput, tail latency, thermals, power, and recovery from link or device faults.
- Leaving power to the end: Qualify regulators, controllers, monitoring, and protection alongside the compute board.
- Assuming a vendor roadmap is supply: Treat projected capacity and future products as plans until qualification and commercial commitments are complete.
What a complete supplier brief should contain
A useful request for quotation or technical evaluation should state the workload, deployment scale, interfaces, capacity targets, performance metrics, power and cooling limits, reliability goals, software environment, qualification tests, delivery schedule, lifecycle expectations, and change-control requirements. Ask suppliers to identify dependencies on package substrates, optical modules, firmware, controllers, and other components. This exposes integration risks that a processor-only comparison misses.
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The best semiconductor supply strategy is consequently a coordinated portfolio: CPUs for control and general-purpose work; HBM and server DRAM for different memory tiers; NAND SSDs for persistence; switching, PCIe, CXL, and optical silicon for data movement; and power-management and conversion devices for stable operation. Accelerators matter, but the surrounding semiconductors determine whether the data centre can turn their theoretical performance into dependable service.
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