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2D semiconductors are atomically thin crystals that can serve as the current-carrying channel in a transistor. Their one- or few-layer thickness gives a gate unusually strong electrostatic control, which could help engineers keep transistors switching as dimensions approach the sub-nanometre scale. Molybdenum disulfide (MoS2) and tungsten diselenide (WSe2) are leading examples.
This is a research direction, not a description of mainstream processors today. Demonstrating a fast transistor or a small circuit is much easier than producing uniform wafer-scale material, low-resistance contacts, reliable insulating interfaces and high-yield chips through a foundry-compatible process. The likely role of 2D materials is as a specialized channel in future scaled logic or vertically integrated devices, potentially alongside silicon rather than as an immediate replacement for every silicon component.
What “two-dimensional semiconductor” means
“Two-dimensional” describes the active material, not the whole chip. A 2D semiconductor is a layered crystal whose electrically useful channel is about one or a few atomic layers thick. It still has finite thickness and sits on, or between, other materials in a transistor stack. The wafer, wiring, package and circuit remain three-dimensional.
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The term does not mean “any atomically thin material.” Graphene is a famous 2D crystal, but ordinary graphene has no convenient band gap for turning a transistor fully off, so it is not interchangeable with a semiconducting TMD in conventional digital logic. A useful question is whether a particular 2D channel provides the required band structure, contacts, reliability and manufacturing path.
Why thickness matters
In a conventional field-effect transistor (FET), a gate voltage controls a channel between source and drain. As the channel becomes shorter, electric fields from the drain can interfere with the gate’s ability to turn the device off. These unwanted effects, commonly called short-channel effects, increase leakage and make a clean logic “0” and “1” harder to maintain.
An atomically thin channel gives the gate a very small distance to control. That geometry can improve electrostatic control and reduce some short-channel problems even when the transistor’s length is extremely small. It does not automatically make a high-performance device: contact resistance, defects, dielectric interfaces and heat removal can dominate the result.
How 2D materials could work in a chip
As the channel of a field-effect transistor
The most direct proposal is to replace the semiconducting channel of a FET with a monolayer or few-layer TMD. A gate electrode, separated from the channel by an insulating dielectric, modulates the carrier concentration. Source and drain contacts inject and collect carriers, while the channel controls the current between them.
Researchers can build top-gated, back-gated and gate-all-around structures. In a gate-all-around design, the gate surrounds the channel more completely, and a naturally thin 2D sheet can complement that geometry. The objective is not simply a thinner transistor, but a device whose switching remains predictable at a scale where a conventional bulk-like channel would lose gate control.
In complementary logic
Useful processors require both n-type and p-type transistors so that complementary logic can switch with low static power. The materials and contact metals do not behave identically: the 2024 Advanced Functional Materials review reports that monolayer MoS2 often tends toward n-type contacts with many elemental metals, while WSe2 often tends toward p-type contacts. Those are observed tendencies, not guarantees for every engineered device. Contact selection, interface chemistry and controlled doping can change the result.
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A practical 2D logic platform therefore needs repeatable complementary devices, not just one excellent n-channel transistor. Researchers are studying contact engineering, dopants and device structures that can produce balanced switching and acceptable threshold-voltage variation.
In vertically stacked and 3D systems
Because a 2D layer is thin, it may be possible to place transistors above completed circuits without consuming the same lateral area. Proposed architectures include complementary FET arrangements and other forms of monolithic 3D integration. Such stacking could increase transistor density or shorten connections between logic layers.
Vertical integration introduces its own constraints. A process used to grow or transfer the upper layer must not damage the lower devices, dielectrics or metal interconnects. Thermal budgets, alignment, vias, heat dissipation and testing become as important as the channel material itself.
Candidate materials and what the numbers mean
MoS2 and WSe2 are frequently discussed because they combine a semiconducting band gap with a layered crystal structure. They are examples of a broad research field, not a settled winning pair. Device behaviour depends on layer count, strain, defects, substrate, dielectric, contacts and processing history.
| Material or example | What is established | How to interpret it |
|---|---|---|
| Monolayer MoS2 | The 2024 Advanced Functional Materials review gives an approximate band gap of 1.8 eV. | This is a value reported by that review for monolayer MoS2, not a universal number for every sample or every 2D semiconductor. |
| Bulk MoS2 | The same review gives an approximate band gap of 1.3 eV. | Reducing the material to a monolayer changes its electronic structure; “MoS2” is not one electrical specification independent of thickness. |
| WSe2 | Frequently studied for p-type behaviour with many elemental-metal contacts. | Contact and doping engineering still determine whether a particular device is reliably p-type. |
| Black phosphorus and InSe | Other layered semiconductors investigated in the literature. | Each has its own stability, contact, integration and performance trade-offs; they are not interchangeable drop-in replacements. |
Band gap alone does not rank transistor materials. A chip process also needs suitable carrier mobility, contact resistance, threshold control, dielectric compatibility, stability in air and under electrical stress, and a manufacturable way to pattern and connect millions or billions of devices.
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A transistor made from a carefully selected flake proves that the physics works. It does not prove that a foundry can make a reliable wafer. The main obstacles are coupled: improving one layer of the stack can worsen another.
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Wafer-scale material quality
Mechanical exfoliation can produce very clean, small flakes, but a flake is not a production wafer. High-volume manufacturing needs growth or deposition over large substrates with controlled layer number, orientation and defect density. Uniformity must hold across the wafer and from lot to lot. Pinholes, wrinkles, grain boundaries and contamination can create large variations in leakage and threshold voltage.
Transfer processes add another risk. Moving a 2D sheet from a growth substrate onto a device wafer can leave residue, tears or trapped bubbles and can misalign the layer with existing structures. Direct growth may avoid some transfer damage but can require temperatures or chemistries that are incompatible with finished circuitry.
Contacts and current injection
Source and drain contacts can limit current even when the channel itself is excellent. A 2D surface has no dangling bonds in the same sense as a conventional three-dimensional semiconductor surface, so simply depositing a metal does not guarantee a low-resistance, ohmic interface. Schottky barriers, short contact lengths and process residues can dominate the measured on-current.
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Contact resistance is especially important as devices shrink: the channel may become shorter while the contact region does not scale favourably. Researchers therefore investigate metal choice, edge contacts, phase engineering, surface treatments and other methods to lower resistance without damaging the channel.
Dielectric interfaces and gate control
The gate dielectric must insulate the channel, tolerate the required voltage and avoid introducing excessive interface traps. Depositing a uniform dielectric on an atomically flat surface can be difficult because the surface may offer few sites for conventional nucleation. An imperfect interface causes hysteresis, mobility loss, threshold shifts and leakage.
Any pretreatment used to help the dielectric grow must be controlled: plasma, chemical functionalization or seed layers can add defects or contamination. A promising transistor result therefore has to be evaluated with the complete dielectric stack, not with the channel in isolation.
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Doping and complementary operation
CMOS-like circuits need predictable n-type and p-type devices. Uncontrolled charge transfer from contacts, substrates or adsorbed molecules can shift the apparent doping and threshold voltage. Intentional doping must be spatially selective, stable during later processing and compatible with the dielectric and contact scheme.
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The 2024 perspective on 2D electronics identifies p-type contacts and controlled doping among the unresolved issues, along with spacers and scalable CMOS-compatible processes. Until those variables are controlled, a demonstration circuit may work but still fail wafer-level yield or lifetime requirements.
Patterning, interconnects and yield
Etching and lithography must define the channel without leaving edge damage or residues. Interconnect metals must survive thermal cycles and make reliable connections to atomically thin layers. A commercial process also needs inspection, repair or redundancy strategies, statistical process control and a way to test devices that are buried in a 3D stack.
Yield is a distribution, not a single best-device measurement. A wafer with a few record transistors is not equivalent to a wafer in which nearly every transistor meets its specification. Foundry-compatible process flows and industry-relevant benchmarks are central requirements identified by the 2025 review Towards fab-compatible two-dimensional electronics.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to judge evidence for 2D chips
Claims about “2D chips” can refer to very different achievement levels. Keep these categories separate:
- Material demonstration: a flake or grown film shows the expected crystal and electronic properties.
- Individual transistor: one or a small number of devices switch and are electrically characterized.
- Small circuit: several devices implement an inverter, memory element or other test function.
- Integrated prototype: a larger circuit demonstrates coordinated operation, but may use research-specific fabrication and limited yield.
- Manufacturable product: a repeatable, qualified process delivers wafer-scale yield, reliability, design rules and economic throughput.
These stages are not interchangeable. A circuit’s transistor count, operating voltage, frequency, endurance and yield should be reported together with the fabrication method and measurement conditions.
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A documented microprocessor milestone
A National Science Review perspective published in 2024 describes a 1-bit MoS2 microprocessor prototype containing 115 transistors in an area of 0.6 mm2. This is an important research-scale integration milestone, but it is not a like-for-like performance comparison with contemporary high-end CPUs, which contain billions of transistors and are manufactured through highly optimized processes.
Where the technology stands today
2D semiconductors are not established as the channel material in mainstream consumer processors. Current research has demonstrated devices and small circuits, while major questions about wafer uniformity, contacts, dielectric integration, doping, thermal management, reliability and process compatibility remain.
The strongest near-term case is selective use where atomic thickness solves a specific integration problem: an ultra-scaled logic channel, a transistor layer stacked over another circuit, or a device whose geometry benefits from close gate control. Whether that advantage outweighs the cost and complexity of introducing a new material into a silicon fab is still an engineering and manufacturing question.
What roadmaps actually predict
A 2024 National Science Review perspective reports an International Roadmap for Devices and Systems (IRDS) projection that places 2D channels at a 0.7 nm technology node in 2034. This is a roadmap forecast cited by that article, not an achieved process node, an announced commercial product or a guaranteed date. Roadmaps express targets under assumed technical progress; they do not remove the fabrication and qualification work needed to reach them.
For readers assessing a future announcement, the most meaningful evidence will be wafer size and uniformity, transistor and circuit yield, contact resistance, operating lifetime, variability, thermal budget and compatibility with established design and manufacturing tools. A smaller “node” label by itself does not establish better system performance.
A practical checklist for comparing 2D chip approaches
- Material and area: Is the film grown uniformly across a wafer, with controlled thickness and defect density, or is the result based on isolated exfoliated flakes?
- Contacts: Are source and drain resistances reported at the short dimensions relevant to the proposed node?
- Gate stack: Which dielectric, interface treatment and leakage measurements support the claimed switching behaviour?
- Doping: Can both polarities be produced predictably, and do they remain stable through subsequent process steps?
- Integration: Are growth, transfer, lithography, spacers, vias and stacking compatible with a realistic CMOS line and thermal budget?
- Reliability: Are variability, bias stress, environmental stability, heat and operating lifetime measured rather than inferred from a short laboratory sweep?
- System evidence: Is the result an isolated transistor, a small demonstration circuit or a functional integrated chip with reported yield?
Bottom line for chip users and investors
2D semiconductors offer a credible way to improve gate control when transistor dimensions become extremely small, and they may enable new vertical integration schemes. MoS2, WSe2 and related layered materials have demonstrated the underlying transistor physics and early circuit integration. The decisive test is manufacturing: uniform films, low-resistance contacts, stable dielectrics, complementary doping, reliable interconnects and high wafer-level yield. Until those pieces are demonstrated together, 2D semiconductors should be understood as a promising research platform for future chips, not as a technology already used throughout ordinary computer processors.
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