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TSMC is the strongest overall answer when “most advanced” means a leading-edge process that is both in production and demonstrated at large customer scale. TSMC says its N2 (2nm) process entered volume production in the fourth quarter of 2025, with good yield and a fast ramp expected in 2026. Samsung Foundry says its SF2 process started mass production in 2025, and Intel says its 18A process entered production in 2025 and high-volume manufacturing in late 2025.
That is not a simple 2nm-versus-18A race. Node names are vendor-specific labels, not directly comparable physical measurements. The practical question is which company combines a cutting-edge transistor process with credible yield, customer shipments, packaging, capacity and a durable manufacturing roadmap. On the public evidence available through 2025, TSMC leads on proven scale and ecosystem. Samsung and Intel are genuine 2nm-class challengers, but the cited public material does not establish the same external-customer volume or directly comparable yield data.
What “most advanced” should mean in a foundry comparison
A process node is only one part of semiconductor capability. A smaller-sounding label can describe a different density target, transistor design, interconnect stack or naming convention at another foundry. Comparing “2nm” with “18A” as if the numbers were ruler measurements can therefore produce a false ranking.
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- Production status: Is the node in risk production, pilot production, mass production or high-volume manufacturing?
- Yield: How consistently do wafers produce working dies at an economically useful rate?
- Transistor architecture: Does the process use a planar, FinFET or gate-all-around approach, and how mature is that implementation?
- Performance, power and density: What improvement does the process offer for a customer’s particular design?
- Customer evidence: Are external customers taping out, shipping products and ordering volume wafers?
- Packaging: Can the foundry combine advanced logic with chiplets, high-bandwidth memory and large-scale integration?
- Capacity and geography: Can it supply the required volume in the regions and time frame a customer needs?
- Design ecosystem and roadmap: Are process-design kits, intellectual-property libraries, tools and follow-on nodes available?
The strongest answer is the company that performs well across those criteria, not necessarily the company with the smallest number in its node name.
At-a-glance comparison
| Foundry | Leading-edge process cited | Public production status | Yield evidence in the cited material | Public scale evidence | What the evidence does not establish |
|---|---|---|---|---|---|
| TSMC | N2 (2nm) | Volume production began in 4Q25; the 2025 annual report says high-volume manufacturing began in 4Q25. | TSMC reports “good yield” and expects a fast 2026 ramp. | 12,682 products, 305 technologies, 534 customers and more than 17 million 12-inch-equivalent wafers of annual capacity in 2025. | No apples-to-apples public table comparing N2 yield, density, wafer price or external-customer volume with SF2 and 18A. |
| Samsung Foundry | SF2 (2nm-class) | Samsung labels SF2 “Started mass production in 2025.” | No directly comparable, independently audited yield figure is provided in the cited pages. | The cited material does not provide a comparable customer count, product count or annual wafer-capacity figure. | Public pages cited here do not quantify external-customer volume, yield, density, wafer pricing or shipment scale. |
| Intel Foundry | Intel 18A | Intel says 18A entered production in 2025 and first went into high-volume manufacturing in late 2025. | No directly comparable yield figure is provided in the cited material. | The cited material establishes production timing but not TSMC-equivalent external-customer scale. | No apples-to-apples public table of yield, density, pricing or external-customer volume. |
The table separates what each company has publicly established from what remains unquantified. “Not stated” does not mean a process lacks the capability; it means the cited public evidence does not support a numerical comparison.
TSMC N2: the clearest evidence of scaled leading-edge manufacturing
Production and yield
TSMC’s official 2nm page says, “TSMC’s 2nm (N2) technology has started volume production in 4Q25 as planned.” Its 2025 annual report adds that N2 “successfully entered high volume manufacturing in 4Q’25, with good yield, and we expect a fast ramp in 2026.” Together, those statements establish more than a laboratory demonstration: the node reached the manufacturing stage in which customer wafers are produced in volume, and TSMC says the initial yield is good enough to support a rapid ramp.
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Scale and customer breadth
TSMC reported 12,682 products made with 305 distinct technologies for 534 customers in 2025. It also reported more than 17 million 12-inch-equivalent wafers of annual capacity. Those figures span the company’s portfolio rather than N2 alone, but they show the manufacturing, logistics and design-support infrastructure surrounding its leading-edge nodes.
The scale matters because advanced chips are difficult to ramp. A process must support mask production, wafer starts, inspection, process control, packaging coordination and reliable delivery while many customers qualify different designs. A large installed base also gives customers more opportunities to reuse design flows, intellectual property and manufacturing relationships across generations.
Industry position
In its 2025 shareholder letter, TSMC said, “Concluding 2025, the Foundry 2.0 industry increased 16% year-over-year.” TSMC also reported 35.9% revenue growth in U.S.-dollar terms for 2025. These are company-reported business figures, not a direct measure of N2 yield or transistor performance, but they indicate strong demand and commercial momentum around the foundry market in which N2 is ramping.
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What TSMC’s public evidence proves—and does not prove
- It proves that N2 reached planned volume and high-volume manufacturing in 4Q25.
- It provides a positive, though qualitative, yield statement and a stated fast-ramp expectation for 2026.
- It demonstrates a much larger disclosed customer and manufacturing footprint than the comparable figures cited for Samsung Foundry or Intel Foundry.
- It does not provide, in the cited material, a side-by-side N2-versus-SF2-versus-18A transistor-density, power-performance, wafer-price or yield table.
Samsung Foundry SF2: a real 2nm-class production contender
Mass production and transistor architecture
Samsung’s logic-node page labels SF2 “Started mass production in 2025.” Samsung describes SF2 as building on a second-generation MBCFET (multi-bridge-channel field-effect transistor) gate-all-around foundation. Gate-all-around transistors surround the channel more completely than older FinFET structures, allowing tighter control of the channel as dimensions shrink. The cited Samsung description establishes the architecture and production claim; it does not, by itself, establish how SF2’s yield compares with N2 or 18A.
Samsung’s process overview describes a foundry portfolio that runs “from 180nm to 2nm and beyond” and highlights EUV and GAA milestones. That breadth is relevant to customers with mixed portfolios: a company may need mature-node analog, radio-frequency or power-management components alongside leading-edge compute dies.
Where the public record is thinner
The cited official pages do not provide a directly comparable, independently audited yield figure for SF2. They also do not provide a table matching TSMC’s 2025 figures for customer count, product count or annual 12-inch-equivalent capacity. Without those numbers, it is not defensible to say that Samsung has a better or worse yield, lower wafer cost or greater external-customer volume than TSMC.
Samsung therefore qualifies as a genuine leading-edge manufacturing alternative, not merely a future announcement. The unresolved question is the breadth and consistency of its commercial ramp relative to TSMC’s already documented scale.
Intel Foundry 18A: production achieved, customer scale still less established
Production timing
An Intel VLSI Symposium update says, “Intel 18A, Intel Foundry’s leading-edge process node, entered into production in 2025.” Intel’s 2025 Form 10-K says 18A “first went into high-volume manufacturing in late 2025” and calls it Intel’s most advanced leading-edge node.
Those statements place 18A in the same broad production-status conversation as N2 and SF2 by the end of 2025. They do not mean that every 18A product was shipping at the same volume, yield or customer diversity as every product on a rival node. Production status is a necessary condition for a leading-edge foundry, not a complete commercial scorecard.
What Intel’s evidence supports
- 18A is Intel Foundry’s most advanced leading-edge process node according to Intel’s 2025 filing.
- The process entered production during 2025.
- Intel says high-volume manufacturing began in late 2025.
- The public statements demonstrate technical ambition and a manufacturing milestone.
The cited evidence does not establish TSMC-equivalent external-customer scale. It also does not provide a directly comparable yield, transistor-density, wafer-price or customer-volume table. Intel may be competitive for a particular design or strategic supply requirement, but a broad claim that 18A is ahead of N2 on manufacturing maturity would go beyond the available evidence.
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Are N2, SF2 and 18A actually equivalent nodes?
No. The labels are useful shorthand within each company’s roadmap, but they do not guarantee identical physical dimensions or transistor density. “2nm” is not a universal specification, and “18A” is a different naming convention. A serious procurement or engineering comparison needs the foundries’ process-design-kit data for the exact product, including standard-cell libraries, SRAM options, interconnect rules, voltage targets, design restrictions and qualification conditions.
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Even a published density number would not settle the question by itself. A chip can trade density for higher frequency, lower voltage, larger cache, better analog behavior or easier yield. The relevant result is the finished design’s performance per watt, die size, defect sensitivity, package configuration and cost at the customer’s target volume.
Which foundry has the best yield?
The cited public material does not support a definitive winner. TSMC is the only one of the three for which these sources explicitly report “good yield” for the named leading-edge node, but that is a qualitative statement rather than a common measurement. Samsung’s SF2 pages and Intel’s 18A statements establish production milestones without publishing comparable yield percentages.
Yield also varies by product. A small, regular compute die, a large cache-heavy die and a mixed-signal design can experience different defect rates on the same process. Customers normally evaluate yield through confidential wafer data, test-chip results, engineering lots and production qualification rather than a single headline number.
Can Samsung 2nm compete with TSMC N2?
Yes, in the sense that Samsung SF2 is presented as a mass-production 2nm-class process using a second-generation gate-all-around architecture. It is a credible technical and commercial alternative. However, the available public evidence favors TSMC when the criterion is demonstrated scale: TSMC discloses N2 high-volume manufacturing with good yield, a fast 2026 ramp expectation, 534 customers across its 2025 business, 12,682 products, 305 technologies and more than 17 million 12-inch-equivalent wafers of annual capacity.
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Is Intel 18A ahead of TSMC N2?
The public production dates do not establish that conclusion. Intel says 18A entered production in 2025 and high-volume manufacturing in late 2025; TSMC says N2 entered volume and high-volume manufacturing in 4Q25 with good yield. Those milestones are close in time, and the companies use different node names and disclose different levels of detail.
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To declare one process technically ahead would require comparable data on density, performance at a defined power target, SRAM scaling, defect density, yield learning, wafer cost and customer products. The cited material does not supply that apples-to-apples set. The defensible distinction is that TSMC currently has stronger public evidence of scaled foundry execution, while Intel 18A is a serious leading-edge production effort whose external scale is less documented in these sources.
Which company can manufacture the most advanced AI chips?
For most readers, TSMC is the best-supported answer today, but “AI chip” is a system description rather than a process-node label. An accelerator’s capability depends on the logic die, memory technology, interconnect, package, thermal design, software and the ability to obtain enough wafers and advanced packaging capacity.
TSMC’s disclosed customer breadth and annual capacity make it the strongest candidate for manufacturing advanced AI logic at broad commercial scale. Its N2 production status is also explicitly documented. Samsung and Intel can be technically relevant for particular AI designs, especially where a customer values a second source or a specific process and packaging combination. The available evidence does not provide comparable external AI-chip shipment volumes for the three foundries, so no company-specific AI market-share conclusion follows from these process announcements alone.
Advanced packaging can change the practical winner
Leading-edge logic is only one part of modern AI and high-performance computing. Large systems often combine multiple compute dies, memory stacks and input/output dies in one package. A foundry’s ability to coordinate wafer fabrication with advanced packaging, testing and supply planning can matter as much as the transistor node.
The supplied company statements do not give a directly comparable table of advanced-packaging capacity, package yields or customer shipment volumes for TSMC, Samsung Foundry and Intel Foundry. Treat packaging as a required due-diligence question rather than assuming that the foundry with the most advanced node automatically offers the best complete system solution.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Capacity and geography: what is publicly measurable
TSMC is the only company in this comparison for which the cited evidence gives a numerical annual capacity: more than 17 million 12-inch-equivalent wafers in 2025. That number covers TSMC’s overall manufacturing network and technology portfolio, not N2 alone. It nevertheless provides a concrete indication of the scale available behind its roadmap.
No directly comparable annual wafer-capacity figures are provided in the cited material for Samsung Foundry or Intel Foundry. A customer requiring geographically diversified supply should request site-specific capacity, qualification status, export-control constraints, backup-fab plans and expected allocation rather than infer those details from a node announcement.
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How to choose a foundry for a real chip project
Use the following sequence instead of choosing by node name alone.
- Define the product requirement. Set the target performance, power, die area, memory configuration, package, annual volume and launch date.
- Shortlist physically suitable nodes. Ask each foundry for the process-design-kit release, standard-cell options, SRAM density, supported voltages and design-rule constraints for the exact product class.
- Verify production status. Distinguish risk production, pilot production, mass production and high-volume manufacturing. Ask when the specific process revision and package will be qualified for your product.
- Request product-specific yield evidence. Review test-chip results, engineering-lot learning, defect-density trends and expected yield for a die of your size and complexity. Do not substitute a corporate-wide yield claim for a product estimate.
- Model total cost. Include masks, wafer price, engineering wafers, packaging, test, scrap, reticle limits, expected yield and capacity reservations. A smaller die is not automatically cheaper if the process or package is harder to qualify.
- Check the design ecosystem. Confirm electronic-design-automation support, intellectual-property availability, interface libraries, memory compilers, multiprocessor interconnect options and the foundry’s technical-support resources.
- Qualify the package and supply chain. Match the logic node with memory, substrate, interposer, assembly and test capacity. Confirm that all parts of the package can ramp together.
- Assess resilience. Review second-source options, geographic exposure, allocation policy, disaster recovery and the roadmap to the next process generation.
- Run a production gate. Require measurable criteria for tape-out, first silicon, yield improvement, reliability qualification and volume shipment before committing the full program.
Common comparison mistakes
Treating node names as physical measurements
“2nm” and “18A” are labels from different roadmaps. Use measured design outcomes and foundry documentation for the specific node instead.
Confusing production entry with mature high-volume output
A node can enter production while still learning yield and ramping capacity. Ask how much of the customer’s required volume is qualified and available, not only whether a press release says “production.”
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Using corporate scale as node-specific yield
TSMC’s 12,682 products, 305 technologies, 534 customers and more than 17 million annual 12-inch-equivalent wafers demonstrate company-wide scale. They are not a published N2-only yield or capacity figure.
Assuming a GAA label settles performance
Samsung’s SF2 uses a second-generation MBCFET GAA foundation, but architecture alone does not reveal the final product’s frequency, power, density or yield. Those outcomes depend on the complete process and design.
Ignoring packaging and memory
An advanced AI accelerator can be constrained by package assembly, memory supply or thermal limits even when the logic wafer is built on a leading-edge node.
Verdict: who is most capable right now?
TSMC is the most defensible overall winner for advanced-chip manufacturing on the public evidence through 2025. N2 reached volume and high-volume manufacturing in 4Q25, TSMC reported good yield and a fast 2026 ramp expectation, and the company disclosed a customer and capacity footprint far larger than the comparable figures available for its rivals.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsSamsung Foundry is a credible 2nm-class challenger. SF2 started mass production in 2025 and uses a second-generation MBCFET gate-all-around architecture, but the cited public pages do not quantify yield or external-customer volume on a directly comparable basis.
Intel Foundry is also a credible leading-edge contender. Intel 18A entered production in 2025 and high-volume manufacturing in late 2025, yet the cited material does not establish the same external-foundry scale that TSMC reports.
If “most advanced” means the smallest-sounding node label, the question has no reliable universal answer. If it means a cutting-edge process that has reached high-volume manufacturing with documented yield, broad customer support and substantial capacity, TSMC is currently the strongest answer.
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