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There is no universal winner between TSMC, Samsung Foundry and Intel Foundry. Choose the manufacturer whose specific qualified process, design kit, yield evidence, packaging flow, capacity reservation, geography and contract terms fit your chip. A label such as “2nm” is not a common performance or cost standard, so begin with your product requirements and compare named process variants rather than corporate roadmaps.
What a foundry decision really covers
A semiconductor manufacturer is not just a wafer supplier. Your choice determines the process design rules, standard-cell and memory libraries, intellectual-property (IP) blocks, design-automation flow, mask costs, wafer economics, yield-learning path, assembly and test route, geographic exposure and the support available when the design fails in the lab. The same company may be an excellent fit for one chip and a poor fit for another.
Start by writing a manufacturing specification before requesting quotations. Include the required performance, power, die area, analog or radio-frequency functions, embedded memory, I/O voltage, automotive or industrial qualification, package, production volume, launch date and acceptable second-source strategy. Then ask each foundry to nominate an exact process revision and site. A generic promise of access to a “2nm,” “3nm” or “18A” family is not sufficient for a tape-out decision.
At-a-glance comparison
| Foundry | Business model and public scale evidence | Publicly described process scope or status | Packaging and integration | Geographic information in the cited sources |
|---|---|---|---|---|
| TSMC | Pure-play foundry; 12,682 products for 534 customers using 305 technologies in 2025; annual capacity above 17 million 12-inch-equivalent wafers in 2025 | N2 volume production began in the fourth quarter of 2025; N2P volume production is scheduled for the second half of 2026 | 3DFabric family of stacking and advanced packaging solutions | Taiwan facilities; subsidiaries in Nanjing, Arizona and Japan; specialty-technology fab construction in Dresden began in 2024; first Kumamoto facility reached volume production at the end of 2024 and a second began construction in 2025 |
| Samsung Foundry | Logic portfolio described from 180nm to 2nm and beyond; public pages also list specialty technologies | Leading-edge and specialty logic, including embedded non-volatile memory, RF, CMOS image sensors, high voltage and BCD | Advanced heterogeneous integration, turnkey packaging and Multi Project Wafer (MPW) prototyping | Samsung describes integrated U.S. and Korean sites as a multi-continent manufacturing network |
| Intel Foundry | Worldwide wafer fabrication, assembly and test; external foundry business is being developed alongside Intel’s own products | Intel 18A entered high-volume manufacturing in late 2025; Intel 3 and Intel 16 are listed offerings; 14A is in active development and seeking external customers | 2D, 2.5D and 3D interconnects; EMIB and Foveros packaging initiatives; assembly and test services | Public manufacturing information describes worldwide sites; the exact site for a customer process must be confirmed contractually |
Sources: TSMC 2025 Annual Report, TSMC technology page, Samsung process technology, Samsung manufacturing, Intel manufacturing and Intel 2025 Form 10-K.
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TSMC: the scale and pure-play benchmark
What the public record establishes
TSMC describes itself as a pure-play foundry: it manufactures customer products and does not design, manufacture or market semiconductor products under its own brand. Its 2025 Annual Report records 12,682 products for 534 customers across 305 distinct technologies. It also reports annual capacity above 17 million 12-inch-equivalent wafers in 2025. Those are company-wide historical measures, not a guarantee that a new customer can obtain starts at a particular node or site.
The same report says 74% of wafer revenue came from 7nm-and-smaller processes in 2025. This demonstrates substantial experience with advanced nodes, but revenue mix is not a substitute for your own design’s yield, price or schedule forecast.
Roadmap status and how to interpret it
TSMC states that N2 volume production began in the fourth quarter of 2025 and describes N2 as using first-generation nanosheet transistors. Its current technology page schedules N2P volume production for the second half of 2026. The first statement is a dated production status; the second is a plan. Confirm the process revision, PDK release, IP qualification, risk-production date and capacity allocation for your design instead of treating the roadmap date as a delivery commitment.
TSMC’s process pages include vendor-generated performance comparisons. Use them to identify questions, then request process-specific design data, reliability evidence and qualification conditions under confidentiality. A headline improvement in a company chart may use a different library, voltage, SRAM configuration or design objective than your product.
Footprint and advanced packaging
TSMC reports facilities in Taiwan and subsidiaries in Nanjing, Arizona and Japan. It began construction on a specialty-technology fab in Dresden in 2024. The report says Japan Advanced Semiconductor Manufacturing’s first Kumamoto facility began volume production at the end of 2024 and a second facility began construction in 2025. Ask which legal entity, fab and assembly/test partners would handle your wafers and whether a design can be transferred between qualified sites.
For systems using chiplets, high-bandwidth memory or stacked dies, TSMC’s 3DFabric family is relevant because it addresses stacking and advanced packaging as part of the manufacturing flow. You still need to verify interposer or substrate availability, thermal limits, known-good-die criteria, test insertion and ownership of package qualification.
Samsung Foundry: broad logic and specialty options
Process breadth
Samsung describes a logic portfolio ranging from 180nm to 2nm and beyond. Its specialty list includes embedded non-volatile memory, RF, CMOS image sensors, high-voltage and BCD technologies. That range can matter when one product combines a digital core with analog, power-management, sensing or radio functions, or when a mature node is more economical than a leading-edge node.
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Samsung’s published performance, power and scalability statements are the company’s own descriptions. They do not establish an independent comparison with TSMC or Intel. Request PPA results using your netlist, the intended operating corners, the same memory density and the same package assumptions before selecting a process.
MPW prototyping and production transition
Samsung offers Multi Project Wafer services for design and IP validation and prototyping. Multiple designs share wafer and mask costs, which can reduce the cash required for an early test chip. An MPW shuttle is useful only if its process, design rules, device options and IP are compatible with the eventual production flow.
Ask four specific questions before using MPW:
- Which exact process revision and fab will run the shuttle?
- Are the same PDK, standard cells, memory compilers and I/O options available for volume production?
- What additional reliability, automotive or security qualification is required after the prototype?
- How are known-good dies, wafer sort, assembly and package-level tests handled when moving from shuttle to dedicated wafers?
Manufacturing network and evidence limits
Samsung says its integrated U.S. and Korean sites form a multi-continent manufacturing network. That can support geographic planning, but the public manufacturing page does not establish comparative yield, available capacity or delivery performance for a particular process. Obtain a site-specific capacity statement, transfer plan and recovery procedure rather than assuming that every listed site can run every process option.
Intel Foundry: manufacturing plus packaging, with roadmap conditions
18A production evidence
Intel’s 2025 Form 10-K says Intel 18A entered high-volume manufacturing in late 2025, uses RibbonFET and PowerVia, and is used in the company’s first Core Ultra Series 3 processor. This is evidence of an internal product and production milestone. It does not, by itself, establish the qualification record, yield or delivery performance of an external customer’s design.
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14A and later nodes require milestone protection
The same 2025 Form 10-K describes 14A as in active development and says Intel is seeking external customers. It also identifies a material risk: if Intel cannot secure significant external demand and meet milestones, it may pause or discontinue 14A and later leading-edge development. A contract for a future node therefore needs explicit milestone definitions, cancellation rights, mask and redesign treatment, and a fallback process.
Packaging and ecosystem
Intel describes 2D, 2.5D and 3D interconnects and packaging, with initiatives including EMIB and Foveros. This integrated path can be attractive when the product needs bridge-based chiplets, stacked dies, assembly and test from one manufacturing organization. Compare the complete flow: die-to-die interface, interposer or bridge supply, substrate, thermal design, package test, burn-in, known-good-die policy and responsibility for field returns.
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Node names are vendor labels
Modern node names are not a shared physical measurement. Two processes carrying the same nominal label can differ in transistor architecture, contacted poly pitch, metal pitch, SRAM density, allowable voltage, design rules, libraries and yield maturity. A smaller label does not automatically mean a smaller die, lower power, higher frequency or lower cost.
Compare the metrics that affect your chip
- Performance: frequency at the required voltage and temperature, including worst-case corners and package parasitics.
- Power: active, leakage and power-density limits for the real workload, not a single marketing operating point.
- Area: standard-cell density, SRAM bit-cell size, analog keep-outs, I/O ring and package constraints.
- Design rules: routing restrictions, via rules, density requirements, electromigration limits and sign-off decks.
- IP: memory compilers, PCIe or other interfaces, security blocks, RF devices, high-voltage devices and third-party hard macros qualified on the exact revision.
- Yield: defect-density learning, redundancy options, wafer-sort coverage and the statistical assumptions behind the cost model.
Require each candidate to run an apples-to-apples feasibility study using the same RTL or representative blocks, target frequency, voltage range, memory capacity, package and production assumptions. Keep process claims separate from measured results on your design.
A step-by-step selection method
- Freeze the product specification. Record performance, power, die-size, memory, analog/RF, I/O, package, qualification, volume and launch requirements. Mark which requirements are hard limits and which can move.
- Create a candidate process list. Name the exact process variant, revision, fab, MPW or dedicated-wafer path, and intended package for each foundry. Do not score a corporate family without a process identifier.
- Check design enablement. Obtain the PDK release, design-rule manual, standard-cell and SRAM views, I/O libraries, sign-off decks, EDA-tool versions and IP qualification status. Confirm that all are supported for the product lifetime.
- Request a PPA and manufacturability study. Supply representative blocks or a restricted netlist and require assumptions for voltage, frequency, utilization, memory, temperature, package and test. Ask for sensitivity ranges rather than one optimistic point estimate.
- Validate production maturity. Classify the process as development, risk production, customer tape-out, qualification or high-volume manufacturing. Ask for comparable yield and reliability evidence under NDA, plus the change-control and excursion-reporting process.
- Reserve capacity and define remedies. Request available starts, wafer lead time, cycle time, ramp assumptions, allocation priority, minimum commitments and remedies if a milestone slips. A company-wide capacity number does not reserve wafers for your program.
- Design the package and test path. Confirm assembly site, substrate or interposer, die stacking or bridge technology, thermal limits, wafer sort, final test, burn-in, known-good-die criteria and return analysis. Include package cost and schedule in the first business case.
- Negotiate lifecycle and exit terms. Define process-change notification, last-time-buy rules, product lifetime, migration assistance, IP ownership, confidentiality, audit rights, geographic contingencies and the cost of moving to another qualified process.
The request-for-information checklist
Send the same matrix to all shortlisted foundries so that a polished presentation cannot hide a missing capability.
- Process fit: exact variant, PDK maturity, design rules, SRAM and I/O choices, analog/RF or memory needs, IP availability and projected PPA.
- Production evidence: current lifecycle stage, comparable yield and reliability data, qualification schedule, process-change control and node-lifetime policy.
- Capacity and schedule: starts at the required node and site, reservation terms, ramp assumptions, wafer lead time, cycle time, allocation priority and remedies for missed milestones.
- Economics: wafer price, masks and non-recurring engineering, yield assumptions, packaging and test charges, engineering support, minimum commitments and redesign or migration costs.
- Packaging and system integration: interposer or bridge supply, chiplet stacking, high-bandwidth-memory support, substrate constraints, assembly/test ownership, thermal and mechanical limits and known-good-die flow.
- Geography and resilience: actual wafer and assembly/test sites, export-control and jurisdiction implications, logistics, disaster recovery, site qualification and desired geographic diversification.
- Customer model and IP: confidentiality boundaries, competing-product information barriers, IP ownership, audit rights and executive escalation paths.
- Ecosystem: EDA flow, libraries, IP blocks, design services and packaging partners enabled on the exact process revision and supported through the intended product lifetime.
Packaging, assembly and test can outweigh the front-end node
For a monolithic low-power controller, wafer process may dominate the decision. For an accelerator, networking device or chiplet system, package bandwidth, thermal resistance, substrate supply and test coverage can set the practical limit. Compare the foundry’s front-end process and back-end route as one qualification plan.
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Economics and contracts
Public materials for these three companies do not provide directly comparable wafer prices, mask charges, yield assumptions or packaging quotes. Build a full cost model from vendor proposals. Include masks, engineering wafers, MPW or shuttle fees, dedicated starts, wafer sort, assembly, substrates, final test, burn-in, logistics, inventory, failure analysis and the cost of a respin.
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Separate one-time and recurring costs. A process with a higher mask bill can still be cheaper at volume if it meets PPA in a smaller die or yields better. Conversely, a low initial MPW fee may not reduce total cost if production requires a different process, new IP qualification and a second package qualification.
Contracts should identify the process revision and site, acceptance criteria, capacity reservation, delivery windows, change-notification period, yield or quality remedies, confidentiality obligations, IP ownership, export controls, force-majeure treatment and termination or migration assistance. For an announced node, tie payments and commitments to measurable PDK, risk-production, qualification and volume milestones.
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Map every step, not just the wafer fab: mask shop, wafer fabrication, probe, assembly, substrate, final test and logistics hub. Ask whether a second site is genuinely qualified for the same design or merely part of the corporate network. Confirm transfer time, reticle compatibility, IP and PDK differences, customer requalification requirements and regulatory approvals.
Evaluate export-control exposure, local-content rules, disaster recovery, utility redundancy, transportation routes and the location of failure analysis. Geographic diversity is useful only when the alternate route can produce an equivalent, qualified product within your required recovery time.
When each foundry belongs on the shortlist
Shortlist TSMC when scale and a mature pure-play ecosystem dominate
TSMC is the strongest initial candidate when you need a broad customer ecosystem, extensive advanced-node production evidence, multiple technology options and a pure-play model without the foundry marketing its own competing chip products. Validate actual capacity, IP readiness, package availability and the specific site rather than relying on the company-wide scale figures.
Shortlist Samsung Foundry when specialty integration or MPW access is central
Samsung deserves early consideration when the design combines logic with embedded memory, RF, imaging, high-voltage or BCD functions, or when an MPW shuttle can reduce prototype cost and schedule. Make the prototype-to-production path a formal gate: the shuttle’s process, site, IP and qualification must match the planned volume flow.
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Shortlist Intel Foundry when integrated packaging and a qualified Intel process fit
Intel is compelling when assembly and test, 2D/2.5D/3D integration, EMIB or Foveros and a compatible Intel process are important system requirements. Treat 18A’s internal high-volume milestone as encouraging but not equivalent to an external-customer reference. For 14A and later nodes, require contractual protection against roadmap changes and confirm external-customer milestones before committing.
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Common selection mistakes and how to correct them
Choosing the smallest advertised node
Failure: selecting a node label before checking analog devices, SRAM, I/O, package and yield. Correction: run the same representative design through feasible process candidates and compare total cost, PPA and schedule.
Confusing internal production with external qualification
Failure: treating a foundry’s own chip at high-volume manufacturing as proof that an outside design will ship on time. Correction: request external-customer evidence, PDK and IP status, qualification data and a milestone plan specific to your design.
Assuming a network means interchangeable fabs
Failure: assuming another site can take over after a disruption. Correction: verify site qualification, transfer rules, reticles, process matching, assembly/test compatibility and recovery lead time in the contract.
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Leaving packaging until after tape-out
Failure: discovering too late that the substrate, interposer, thermal solution or test flow cannot support the die. Correction: co-design package and test constraints during architecture and include package yield in the business case.
Accepting an unbounded roadmap promise
Failure: paying for a future node without measurable deliverables. Correction: define PDK, risk-production, qualification and volume milestones, with remedies and a qualified fallback process.
A practical scoring framework
Use a weighted score only after minimum requirements are passed. A candidate that fails an essential IP, qualification, package or launch-date requirement should be rejected regardless of its total score.
| Gate | Evidence to require | Decision question |
|---|---|---|
| Technical fit | Process-specific PPA study, design rules, memory and I/O options | Can the chip meet performance, power and area targets with acceptable design risk? |
| Enablement | PDK release, sign-off decks, qualified IP and tool versions | Can the team complete implementation and sign-off on the intended revision? |
| Manufacturing maturity | Lifecycle stage, yield-learning data, reliability and qualification plan | Is the process mature enough for the product’s launch and lifetime? |
| Capacity | Site-specific starts, allocation, lead time and ramp assumptions | Are wafers contractually available when production needs them? |
| Package and test | Package design rules, substrate plan, assembly/test flow and thermal data | Can the complete product be built and tested at the required volume? |
| Commercial risk | Wafer, mask, package and test quotes; commitments and remedies | Is total cost predictable, and is there a remedy for missed milestones? |
| Resilience | Site map, transfer plan, logistics and disaster recovery | Can supply continue after a site, geopolitical or logistics disruption? |
Bottom line for a buying team
Use TSMC as the scale and pure-play benchmark, Samsung as a broad logic-and-specialty candidate with an MPW prototyping route, and Intel as an integrated manufacturing, packaging and test option whose external-foundry roadmap needs close milestone scrutiny. The final choice should come from a process-specific, design-specific proposal that proves PPA, IP readiness, yield path, package capability, capacity and contractual protection. If a vendor cannot answer those questions for your exact chip, its node label and corporate scale are not enough to justify selection.
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