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Neither foundry is a universal winner. TSMC offers the clearest public evidence of very large aggregate capacity, while Samsung has a current public statement that its SF2 node entered mass production in 2025 and operates fabs in Korea and the United States. TSMC’s N2P and A16 are scheduled for volume production in the second half of 2026, not confirmed as already ramped in the available company material. For a real chip program, the decision turns on qualified capacity for the exact process, PPA results, PDK and IP maturity, packaging, geography, schedule confidence and commercial terms—not on whether a node name says “2nm” or “3nm.”
What the comparison can—and cannot—tell you
“TSMC vs. Samsung Foundry” sounds like a conventional technology contest, but a foundry decision is a supplier-fit exercise. A node label is a generation name chosen by a company. It is not a universal measurement of gate length, transistor density, performance, power, cost or yield. Two processes carrying similar labels can require different design rules and deliver different results on the same chip.
The public evidence available for this comparison is also asymmetric. TSMC publishes a company-wide annual-capacity figure. Samsung’s current public material describes its manufacturing network and process status but does not provide a directly comparable aggregate capacity number. Neither company’s public sources reviewed here establish comparable process-specific yield, utilization, wafer pricing or lead-time statistics.
That means the responsible conclusion is conditional: establish which process is qualified for your design and date, then obtain fab-level allocation and commercial evidence from each supplier. Treat public roadmap dates and capability descriptions as inputs to diligence, not as a procurement commitment.
#1 Best Overall
- COMPATIBILITY: Development board supporting multiple wireless protocols including Bluetooth
- Thread, Matter, Zigbee, ANT, and NFC at 2.4GHz frequency
- PROCESSOR: Features the advanced nRF54L15 transceiver chip from Nordic Semiconductor for reliable wireless communications
- WIRELESS STANDARDS: Implements IEEE 802.15.4 protocol support for Matter, Thread, and Zigbee networking applications
- DEVELOPMENT PLATFORM: Comprehensive evaluation board designed for testing and prototyping wireless connectivity solutions
Process-node status in 2025 and 2026
Samsung Foundry: SF2 is listed as in mass production
Samsung Semiconductor’s current logic-node page says SF2 “Started mass production in 2025.” Samsung describes SF2 as its second-generation MBCFET (gate-all-around, or GAA) process and lists mobile, high-performance computing (HPC), artificial intelligence and automotive applications. The same page lists SF3 mass production from 2022 and SF4 from 2021.
“Started mass production” is a status statement, not a disclosure of wafer volume, customer yield, utilization or the number of products shipping on SF2. It confirms that Samsung presents the process as a production node; it does not prove that a particular customer can receive the capacity, IP or schedule needed for a new design.
TSMC: N3 variants in production, N2P and A16 scheduled
TSMC’s official technology material says N3X started volume production in 2025 and N3C in 2026. Its 2025 annual-report material schedules N2P and A16 volume production for the second half of 2026. Those dates are company schedules. They should not be rewritten as evidence that volume production had already begun by the October 2026 information date unless TSMC provides a newer, direct confirmation.
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Roadmap versus verified application availability
Samsung’s 2023 application timetable
Samsung’s June 2023 roadmap planned SF2 mobile mass production in 2025, expansion to HPC in 2026 and automotive in 2027. The current logic-node page confirms the 2025 mass-production status for SF2, but the later HPC and automotive milestones remain dated roadmap plans in the public material considered here. Do not describe those application ramps as completed production milestones without a current, product-specific confirmation.
Samsung positions its foundry services for HPC, mobile and 5G, automotive and IoT. It also describes support for libraries, process-design kits (PDKs), design methodology, intellectual property, packaging, cloud services and ecosystem partners. These are Samsung’s descriptions of the services it offers; they are not independent measurements of yield, schedule or cost.
TSMC’s scheduled N2P and A16
TSMC’s published second-half-2026 schedule for N2P and A16 is useful for planning, but a scheduled date is not the same as a completed ramp. A customer should request the current PDK release, design-rule maturity, silicon-learning status, qualification criteria and committed wafer-start plan before selecting either process for a product with a fixed launch date.
Rank #2
- DEVELOPMENT BOARD: Nordic Semiconductor NRF52-DK development and evaluation board designed for wireless applications and prototyping
- WIRELESS CAPABILITIES: Features Bluetooth
- (BLE) and ANT protocol support with 2.4GHz operation frequency for versatile connectivity options
- PROCESSOR OPTIONS: Compatible with both nRF52810 and nRF52832 transceivers, offering flexibility for different project requirements
- NFC SUPPORT: Includes Near Field Communication (NFC) capabilities, expanding potential use cases and application scenarios
Capacity and manufacturing geography
TSMC’s disclosed aggregate capacity
TSMC’s 2025 annual-report website reports annual capacity of more than 17 million 12-inch-equivalent wafers across facilities managed by TSMC and its subsidiaries in 2025. This is the strongest current numerical capacity figure in the public material used for this comparison.
The number covers the company’s managed facilities and is company-wide. It is not a leading-edge-only figure, does not identify capacity by node or fab, and does not mean that 17 million wafers are available to a new customer. Allocation may already be committed, constrained by a particular process step or packaging line, or limited by qualification and scheduling requirements.
Samsung’s network description
Samsung describes an integrated manufacturing network spanning Giheung, Hwaseong and Pyeongtaek in South Korea, together with Austin and Taylor in the United States. The company says the network supports both legacy and advanced semiconductors.
The reviewed Samsung material does not provide a current total-capacity figure directly comparable with TSMC’s more-than-17-million-wafer disclosure. Site count, announced investment or older expansion plans cannot be converted into a reliable wafer-capacity ratio. The honest public comparison is therefore asymmetric: TSMC discloses an aggregate number; Samsung provides a geographic and capability description without an equivalent total.
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- Qualified wafer starts for the exact process and fab, by quarter.
- Available allocation after existing commitments, including ramp assumptions.
- Expected cycle time from wafer start through probe, assembly and final test.
- Second-source or alternate-fab feasibility for the same design and package.
- Contingency plans for equipment outages, logistics disruption or a delayed ramp.
- Capacity for advanced packaging and interconnect, not only front-end wafer fabrication.
A company-wide wafer figure supplies context. It is not a capacity quotation or a guarantee that a design can be moved into production when needed.
How node names affect a real chip design
Why “2nm” is not a universal measurement
Process-generation names communicate a broad technology generation, but they do not specify every physical dimension or electrical characteristic. The relevant comparison for a customer is the process’s measured performance, power and area (PPA) on that customer’s architecture, under comparable voltage, frequency, temperature, library and packaging conditions.
A process may be attractive on one axis and weaker on another. A high-density option can reduce die area but impose design-rule or routing constraints. A performance-focused variant may meet frequency targets with a different power or cost profile. GAA transistor architecture, backside or interconnect choices, SRAM behavior, analog options and available libraries can all change the result.
Rank #3
- EVALUATION BOARD: NRF9151-DK development board from Nordic Semiconductor designed for cellular IoT and GNSS applications
- CONNECTIVITY: Features both cellular connectivity and GNSS (Global Navigation Satellite System) capabilities for location-based applications
- DEVELOPMENT PLATFORM: Ideal for prototyping and testing IoT devices, supporting cellular network communications
- COMPATIBILITY: Designed to work with Nordic Semiconductor's development tools and software development kit
- APPLICATIONS: Perfect for creating IoT solutions, asset tracking systems, and location-aware connected devices
The evidence needed to compare PPA
- A current PDK and the exact standard-cell, memory and interface IP versions planned for the design.
- Foundry-provided design rules, extraction models and sign-off decks.
- Power, timing, area and thermal results from the customer’s representative blocks, not a generic node chart.
- Silicon data from the process and package combination that will ship.
- Qualification limits for voltage, temperature, reliability and automotive or other sector requirements.
Without those inputs, declaring one company’s “2nm” faster, smaller, lower power or cheaper than the other’s would exceed the public evidence.
Customer and application fit
Mobile and consumer devices
Mobile programs often prioritize power efficiency, die area, modem and memory IP, predictable ramp timing and package cost. Samsung explicitly places SF2 in mobile applications and reports its mass-production start in 2025. A customer should still verify the mobile-specific IP portfolio, PDK maturity, wafer allocation and package qualification for its product rather than infer readiness from the node label.
HPC and AI accelerators
HPC and AI designs typically stress frequency, power delivery, die size, reticle limits, high-bandwidth memory integration and advanced packaging. Samsung lists SF2 for HPC and AI applications. TSMC describes a broad foundry portfolio that includes advanced and specialty processes, advanced mask technology and 3DFabric packaging. Those descriptions make both suppliers candidates for evaluation; they do not establish that either will produce a particular accelerator at a lower cost or higher yield.
Automotive and long-life products
Automotive programs place unusual weight on qualification, long-term supply, traceability, change control, operating temperature and geographic resilience. Samsung’s 2023 roadmap associated SF2 automotive expansion with 2027, but that timetable is historical roadmap context rather than proof of a completed automotive ramp. Obtain the current qualification plan, production site, longevity commitment and quality metrics for the exact automotive part.
IoT and mixed-node systems
Many IoT products do not need the newest logic generation. Specialty analog, radio-frequency, embedded memory, high-voltage or low-leakage options can matter more than minimum geometry. TSMC says its portfolio includes advanced and specialty technologies; Samsung describes support for legacy as well as advanced semiconductors. Compare the complete system bill of materials and package, not only the leading-edge logic node.
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TSMC’s stated ecosystem scope
TSMC’s annual-report material describes advanced and specialty process technologies, advanced mask technology, 3DFabric packaging, manufacturing productivity and design-ecosystem support. It also says capacity planning is conducted with customers. For a chiplet or large accelerator, that means packaging capacity, substrate availability, interconnect technology and assembly sequencing belong in the same sourcing decision as the wafer process.
Samsung’s stated design and manufacturing support
Samsung describes design support spanning libraries, PDKs, design methodology, IP, packaging, cloud services and partner support. Its network description covers Korean and US manufacturing locations. A customer should ask which of these services are qualified for the selected node, which are supplied by partners, and whether the required package can be built at the same location and schedule as the wafers.
Rank #4
- Development Platform: nRF52833-DK evaluation board designed for prototyping and testing Bluetooth
- BLE, Thread, and Zigbee applications using the nRF52833 SoC
- Wireless Connectivity: Supports multiple protocols including Bluetooth
- (BLE), 802.15.4 (Thread, Zigbee) operating at 2.4GHz frequency for versatile wireless development
- Integrated Antenna: Features PCB trace antenna built directly on-board for immediate testing and development without requiring external antenna components
Broadcom collaboration: a signal, not a production proof
On July 25, 2026, Samsung announced a memorandum of understanding with Broadcom covering collaboration on 2nm-and-below foundry technologies and advanced packaging, including work related to Broadcom products. This is a named partnership signal and may be relevant to customers assessing Samsung’s ecosystem. An MOU is not confirmation that a specific Broadcom chip has entered production, nor is it a general endorsement applicable to every customer.
What NVIDIA’s supplier disclosures establish
NVIDIA’s fiscal 2025 Form 10-K says it uses foundries including TSMC and Samsung to produce semiconductor wafers and describes supplier relationships as a source of redundancy and resilience. This establishes that both companies are suppliers to a major chip company at the corporate level.
The filing does not identify the process or foundry used for every NVIDIA product. It therefore cannot support a product-by-product ranking of the two suppliers, nor does it reveal the capacity, yield or commercial terms NVIDIA receives for any particular design.
Side-by-side public facts
| Area | TSMC | Samsung Foundry |
|---|---|---|
| Current advanced-node status cited here | N3X volume production stated for 2025; N3C volume production stated for 2026. | SF2 mass production stated as started in 2025; SF3 listed from 2022 and SF4 from 2021. |
| Next-generation schedule | N2P and A16 volume production scheduled for the second half of 2026 in 2025 annual-report material. | SF2 expansion to HPC in 2026 and automotive in 2027 comes from a 2023 roadmap; the current page confirms SF2 status but not completion of those later application ramps. |
| Public aggregate capacity figure | More than 17 million 12-inch-equivalent wafers of annual capacity across TSMC-managed facilities and subsidiaries in 2025. | A directly comparable current total is not provided in the material considered here. |
| Manufacturing geography described | Annual-report material covers facilities managed by TSMC and subsidiaries; the cited figure is company-wide. | Giheung, Hwaseong and Pyeongtaek in Korea, plus Austin and Taylor in the United States. |
| Service and ecosystem description | Advanced and specialty processes, advanced mask technology, 3DFabric packaging, manufacturing productivity and design-ecosystem support. | Libraries, PDKs, design methodology, IP, packaging, cloud services and partner support; legacy and advanced manufacturing. |
| Named customer or partner signal | NVIDIA’s fiscal 2025 Form 10-K lists TSMC among its foundry suppliers. | NVIDIA’s fiscal 2025 Form 10-K lists Samsung among its foundry suppliers; Samsung announced a July 25, 2026 MOU with Broadcom on 2nm-and-below technologies and advanced packaging. |
The table contains company-reported status and descriptions, not a controlled benchmark. It does not establish comparable yield, utilization, pricing, lead time, performance or market share.
A practical foundry-selection procedure
- Freeze the product requirements. Record target performance, power, die area, package, memory interfaces, operating conditions, launch date and required product lifetime.
- Shortlist qualified processes. Ask each foundry whether the exact node, variant, IP and package are in production, risk production or design enablement for your target tapeout date.
- Run the same representative design. Use equivalent libraries, constraints, voltage assumptions and package conditions to compare PPA. Require sign-off-quality models rather than marketing charts.
- Audit enablement. Check PDK release maturity, design-rule stability, standard-cell and memory options, interface IP, extraction and sign-off decks, EDA interoperability and technical support.
- Request a capacity plan. Obtain fab- and process-specific wafer starts by quarter, allocation rules, ramp assumptions, cycle-time targets and the capacity of required packaging and test operations.
- Validate qualification and quality. Review reliability data, qualification plans, change-control procedures, failure-analysis support and sector-specific requirements such as automotive longevity.
- Assess resilience. Map fabrication and packaging locations, logistics routes, export or customer-location requirements, alternate-fab options and recovery plans for disruption.
- Negotiate commercial commitments. Compare wafer price, mask costs, non-recurring engineering, minimum commitments, expedite terms, yield treatment, engineering-change costs and warranty or quality provisions.
- Make the decision against the launch risk. Select the supplier whose verified process, capacity and support meet the product’s schedule and economics. A nominally newer node is not preferable if it misses qualification or allocation needs.
Questions to put in the supplier request
- What is the current production status of the exact process variant, and which fab will run the wafers?
- Which PDK, IP and design-rule revisions are considered production-ready for a tapeout on the proposed date?
- What wafer-start allocation is available to this program in each quarter, and what assumptions support that allocation?
- Which yield metric will be reported, at what maturity point, and how will yield learning affect delivery?
- What package, interposer, chiplet or memory-integration capacity is available, and where is it located?
- Can the design be qualified at a second site or transferred to another fab without a new full design cycle?
- What are the committed cycle time, change-control process, quality reporting and escalation path?
- Which customer references or silicon examples are relevant to the same process, package and application class?
Common comparison mistakes
Treating the smallest node number as the winner
Node names are not equivalent physical measurements. Choose using measured PPA, IP availability, qualification and total program risk.
Turning a roadmap date into a production fact
TSMC’s second-half-2026 N2P and A16 dates are scheduled milestones. Samsung’s 2023 HPC and automotive expansion dates are roadmap context. Confirm current production and allocation with the supplier.
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TSMC’s more-than-17-million-wafer figure includes all company-managed capacity and all process generations. It does not reveal leading-edge allocation for a new account. Samsung’s lack of a comparable public total means no defensible capacity ratio can be calculated.
Best Value
- DEVELOPMENT KIT: Nordic Semiconductor NRF5340-AUDIO-DK designed for audio application development with nRF5340 dual-core Bluetooth LE SOC
- VERSATILE CONNECTIVITY: Features multiple interface options including I2S, SPI, UART, and USB for comprehensive development capabilities
- POWER SPECIFICATIONS: Operates with flexible power supply range of 1.7V to 5V, suitable for various development scenarios
- TEMPERATURE RANGE: Capable of operating in environments up to +105°C, ensuring reliable performance across diverse conditions
- AI COMPATIBILITY: Supports Edge Impulse platform integration, enabling advanced machine learning and AI development capabilities
Using a customer name as a process endorsement
NVIDIA’s filing establishes that both companies are foundry suppliers at the corporate level, not that every NVIDIA product uses both or that one supplier is superior. The Broadcom announcement is an MOU, not proof of a completed production ramp.
Ignoring packaging and geography
A wafer can be available while the required advanced package, substrate, memory integration or delivery location is constrained. Include the entire manufacturing chain in the sourcing plan.
Decision guidance by situation
Choose TSMC first for evaluation when
- You need a supplier with a clearly published, very large aggregate capacity base and want to investigate allocation within that network.
- Your design depends on TSMC’s stated advanced-process, specialty-process or 3DFabric ecosystem.
- Your schedule aligns with a currently supported TSMC production node, or you can manage the qualification risk of a scheduled future node.
These are screening conditions, not a guarantee of lower price, higher yield or faster delivery.
Choose Samsung first for evaluation when
- SF2’s stated GAA architecture and 2025 mass-production status align with the design’s mobile, HPC, AI or automotive requirements.
- A Korean or US manufacturing footprint and Samsung’s described design, IP and packaging support fit the program’s resilience and integration needs.
- The Broadcom collaboration or another confirmed ecosystem relationship is relevant to the exact technology and package you need.
These signals still require process-specific PPA, capacity, qualification and commercial verification.
Keep both suppliers in the running when
- The product has enough schedule flexibility to complete equivalent silicon and package evaluations.
- Supply resilience or second-source options matter more than a single headline metric.
- The required performance can be met on more than one process generation and the final choice depends on allocation or economics.
Bottom-line interpretation
Public information supports three firm conclusions. Samsung currently presents SF2 as having started mass production in 2025. TSMC reports more than 17 million 12-inch-equivalent wafers of annual capacity across its managed facilities and subsidiaries for 2025, while the available Samsung material does not provide a comparable total. TSMC’s N2P and A16 are scheduled for volume production in the second half of 2026, which remains a schedule rather than an observed completed ramp in the cited material.
Everything that determines the best supplier for an individual chip—PPA on the customer’s design, qualified capacity, yield learning, IP and PDK maturity, package availability, geography, price and delivery commitments—must be established at program level. Use the public roadmap and capacity disclosures to build the shortlist, then make the decision from supplier evidence tied to your tapeout and launch dates.
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