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TSMC and Samsung Foundry are both credible choices for advanced and specialty chips, but the public evidence does not support naming one a universal winner. TSMC discloses unusually detailed 2025 shipment, capacity, customer and process-roadmap figures. Samsung’s foundry materials emphasize a wide technology portfolio, design support and integrated packaging, without publishing matching capacity, yield, pricing or customer-mix metrics in the materials considered here.
For a chip company, the right decision depends on the exact process, design-kit maturity, intellectual-property (IP) availability, target performance and power, package, qualification plan, manufacturing location and contractual capacity commitment. A “2 nm” or “3 nm” label is not a normalized measurement across vendors, so node names alone cannot settle the choice.
What TSMC and Samsung Foundry actually sell
A foundry manufactures wafers for chip designers that do not operate their own leading-edge fabs. The service includes more than transistor fabrication: process design rules, a process design kit (PDK), standard-cell libraries, memory and interface IP, design-rule checking, manufacturing hand-off, wafer test, packaging options and production support.
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TSMC presents itself as a pure-play foundry with a broad process catalogue and manufacturing footprint. Its 2025 annual report says it supported 12,682 products for 534 customers across 305 distinct process technologies. The same report says annual manufacturing capacity exceeded 17 million 12-inch-equivalent wafers in 2025 and that it shipped 15.0 million 12-inch-equivalent wafers that year.
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Samsung Foundry describes a portfolio that combines advanced logic with specialty technologies and an integrated design-to-package offering. Its public materials cover gate-all-around (GAA), FinFET, fully depleted silicon-on-insulator (FD-SOI) and planar process families, plus radio-frequency, embedded nonvolatile-memory, high-voltage, BCD, image-sensor and fingerprint-sensor options. Samsung also describes design enablement, ASIC design services and 2.5D/3D packaging.
Those descriptions establish different strengths, not a complete head-to-head scorecard. Samsung’s reviewed pages do not provide figures that can be compared directly with TSMC’s wafer shipments, annual capacity, customer count, wafer revenue or reported yields.
Process roadmaps: what is known and what still needs validation
TSMC’s reported near-term schedule
TSMC reported that its N2 process entered high-volume manufacturing in the fourth quarter of 2025. The company said N2P and A16 were scheduled for volume production in the second half of 2026, and A14 was scheduled for 2028. These are TSMC’s reported status and plans; they are not independent forecasts of industry-wide availability.
TSMC’s annual report also states that 3-nanometer technologies represented 24% of its 2025 wafer revenue and that advanced technologies—7 nm and beyond—accounted for 74% of total wafer revenue. C.C. Wei, TSMC’s chairman and chief executive, wrote that “Our 2-nanometer technology successfully entered high volume manufacturing in 4Q’25, with good yield, and we expect a fast ramp in 2026.” “Good yield” is the company’s own characterization of its process, not an independently audited comparison with Samsung.
Samsung’s publicly described process families
Samsung describes advanced GAA and FinFET offerings alongside FD-SOI and planar processes. Its materials focus on the range of applications each family can serve, design ecosystem resources and the way logic, specialty processes and packaging can be combined. The reviewed pages do not give a directly matched timetable for Samsung nodes against TSMC’s N2, N2P, A16 or A14 schedule.
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That absence should not be read as evidence that Samsung lacks a process, customers or production capacity. It means only that the public pages used for this comparison do not disclose period-matched figures or a schedule that can be placed on the same table as TSMC’s reported roadmap.
Why “2 nm” and “3 nm” are not enough
Node names are process-generation labels, not a guaranteed physical gate length or a universal density metric. Two manufacturers can use the same nominal node name while differing in transistor architecture, contacted-poly pitch, metal pitch, standard-cell libraries, SRAM characteristics, voltage options and design rules. A chip that performs well on one process may require substantial redesign to move to another.
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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchAsk each foundry for the exact PDK revision, design-rule manual, library qualification, SRAM compiler status, interface IP list, expected performance and power at the intended voltage, and the tape-out date supported by that release. Confirm whether the process is in risk production, qualification or high-volume manufacturing for your product—not merely announced.
Scale, capacity and manufacturing geography
TSMC’s published operating scale is unusually specific. In 2025 it reported 15.0 million 12-inch-equivalent wafer shipments, more than 17 million 12-inch-equivalent wafers of annual manufacturing capacity, 305 process technologies and 534 customers. These numbers use TSMC’s definitions and reporting period; they should not be compared with a Samsung number unless Samsung reports the same scope, period and wafer-equivalent basis.
TSMC identifies manufacturing operations in Taiwan and subsidiaries or facilities in China, the United States and Japan. Its annual report also discusses a planned specialty fab in Germany. The location available to a customer depends on the selected process and the agreement; a company’s global footprint does not mean every node is produced at every site.
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Samsung describes a global foundry network and identifies Samsung Austin Semiconductor among its manufacturing operations. The public pages reviewed do not state a matching annual wafer capacity, shipment volume or geographic allocation by process.
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| Decision axis | TSMC evidence | Samsung Foundry evidence | What a buyer must confirm |
|---|---|---|---|
| Reported 2025 scale | 15.0 million 12-inch-equivalent wafer shipments; more than 17 million annual 12-inch-equivalent wafer capacity | No directly matched shipment or capacity figure stated in the reviewed public pages | Wafer starts, allocation, ramp curve, yield learning and binding supply commitments |
| Process breadth | 305 distinct process technologies reported for 2025 | GAA, FinFET, FD-SOI, planar and specialty families described | The exact process, options, PDK revision and qualification status for the design |
| Geographic disclosures | Facilities or subsidiaries in Taiwan, China, the United States and Japan; planned specialty fab in Germany | Global foundry network described; Samsung Austin Semiconductor identified | Actual fab, export-control limits, logistics, incentives and geographic redundancy |
Capacity is not simply a headline number. A foundry can have substantial total capacity while a particular advanced node, package, memory stack or automotive-qualified line is constrained. Request a monthly wafer-start plan, committed allocation, ramp assumptions, approved alternate sites and the remedies that apply if supply falls short.
Design enablement and engineering support
Samsung’s SAFE-oriented services
Samsung describes an ecosystem commonly referred to as SAFE, including electronic-design-automation and design-methodology support, third-party IP, a cloud-based design environment and ASIC design services. For a start-up or a team moving from an older node, these services can reduce the number of vendors and integration steps it must coordinate.
Evaluate the offering at the level of your project rather than by logo. Confirm that the required CPU, GPU, interface, security, memory and analog IP is available for the exact process and PDK revision. Ask which EDA tool versions are qualified, who owns integration bugs, how many engineering-support hours are included and what non-recurring engineering charges apply.
TSMC’s ecosystem and customer model
TSMC’s scale and large customer base imply a broad ecosystem, but a customer still needs to verify the specific enablement package. Obtain the current PDK, qualified IP list, reference flows, design-rule waivers, sign-off criteria and support escalation path. TSMC’s annual report says its responsibility as a foundry is to provide advanced technologies and necessary capacity so customers can develop products; that statement expresses the company’s role, not a guarantee for an individual contract.
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Porting effort is a first-order cost
Moving a design between foundries can require new physical implementation, analog redesign, SRAM replacement, timing closure, verification, reliability analysis, package changes and software retuning. Even when RTL is portable, the physical database, libraries and sign-off methodology are not automatically interchangeable. Include engineering time, mask sets, IP relicensing, validation silicon and schedule risk in the comparison instead of looking only at quoted wafer price.
Specialty processes and application fit
Leading-edge logic is not automatically the best process for every product. Samsung lists RF, embedded nonvolatile memory, high voltage, BCD, image-sensor and fingerprint-sensor options. These capabilities matter when a product combines digital logic with analog, power-management, sensing, embedded memory or high-voltage devices.
TSMC says it works with strategic customers on mature-node specialty solutions. A mature node can offer lower mask cost, proven analog behavior, long availability and easier qualification, even when its transistor density is lower than a leading-edge node.
For either supplier, ask for device-level evidence: operating-voltage ranges, analog matching data, memory endurance, RF figures of merit, automotive or industrial qualification, product-lifetime commitments and the process options that can coexist on one die. A specialty feature listed in a portfolio is not proof that it meets your temperature, reliability or performance target.
Packaging and heterogeneous integration
Advanced packaging can determine system performance as much as the wafer process. TSMC lists CoWoS, InFO, SoIC and COUPE development. These technologies address 2.5D interposers, fan-out packaging, 3D stacking and chiplet or optical-interconnect use cases at different points in the roadmap.
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Samsung describes integrated 2.5D and 3D packaging and heterogeneous integration. Its proposition is attractive when logic, memory and other dies must be developed as one package flow, but the customer still needs package-specific capacity and qualification details.
Compare the complete package path:
- Maximum package size, die count and allowable die-to-die interconnects.
- High-bandwidth-memory availability, stack suppliers and substrate allocation.
- Thermal design power, heat-spreader and cooling constraints.
- Known-good-die test, burn-in, final test and failure-analysis ownership.
- Package assembly location, lead time and capacity during ramp.
- Yield interaction between wafer fabrication, die bonding and final assembly.
A process can meet transistor targets and still miss the product schedule if the package, substrate or memory supply is not ready at the same time.
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The public information considered here does not establish a reliable, comparable TSMC-versus-Samsung wafer price, yield or customer-specific delivery schedule. Do not infer those values from a node name or from a company’s total revenue.
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- Base wafer price and price breaks by volume.
- Mask and reticle charges, shuttle or multi-project-wafer fees, and other non-recurring engineering costs.
- Wafer sort, probe, assembly, final test and package charges.
- Expected die yield, test escape assumptions and the definition of a good die.
- Capacity-reservation fees, take-or-pay terms and allocation priority.
- Engineering-change, redesign and mask-respin pricing.
- Currency, taxes, logistics, inventory ownership and payment terms.
- Service-level remedies for missed wafer starts, delayed qualification or unapproved process changes.
Calculate total cost per good packaged unit under conservative, target and upside yield cases. A lower wafer quote can be more expensive if yield learning is slower, the IP requires redesign or packaging capacity is unavailable.
A practical selection process for a chip company
- Freeze the product requirements. Document performance, power, die size, memory, interfaces, operating temperature, reliability grade, expected annual volume, launch date and acceptable unit cost.
- Shortlist process families. Decide whether the product needs leading-edge density, GAA or FinFET logic, FD-SOI, RF, embedded memory, high voltage, BCD, image sensing or another specialty option.
- Check enablement before benchmarking. Obtain the PDK release, design rules, standard-cell and SRAM libraries, required IP, EDA compatibility and sign-off checklist. Eliminate a process that cannot support the tape-out window.
- Model implementation effort. Estimate porting, physical-design, analog-redesign, verification, IP licensing, emulation and validation-silicon work. Include engineering support availability and escalation times.
- Define the package at the same time as the die. Select 2D, 2.5D, fan-out, 3D or chiplet integration, then verify substrate, memory, thermal, test and assembly capacity.
- Request capacity commitments. Ask for the specific fab, wafer starts per month, ramp milestones, alternate-site plan and contractual remedies. Do not substitute a supplier-wide capacity headline for a product allocation.
- Run a total-cost model. Combine masks, wafers, yield, test, packaging, logistics, inventory, engineering changes and schedule risk into cost per good unit.
- Use risk gates. Require evidence at PDK release, IP qualification, first silicon, reliability qualification, package validation and production ramp. Assign an owner and fallback action for each failure mode.
Which option fits common scenarios?
When TSMC may be the stronger starting point
TSMC is a logical first candidate when a project needs the roadmap it publicly reports—N2 high-volume manufacturing from the fourth quarter of 2025, planned N2P or A16 volume in the second half of 2026, or A14 in 2028—and when a large, multi-region manufacturing network and broad reported process scale are important. Those advantages still have to be confirmed for the customer’s exact design, package and contract.
When Samsung may be the stronger starting point
Samsung deserves early consideration when the design benefits from its described GAA, FinFET, FD-SOI or planar choices, specialty processes, ASIC design services, cloud-based design environment or integrated 2.5D/3D packaging. The deciding evidence should be the qualified process, IP and capacity proposal for the product, not the breadth of a marketing portfolio alone.
When neither can be selected from public information
If the project requires a guaranteed launch date, automotive qualification, a specific memory stack, unusual analog performance or a binding price, public pages are insufficient. Run a formal request for proposal with both foundries and require period-specific, design-specific answers.
Pitfalls that produce misleading comparisons
- Comparing node names as physical dimensions. Use density, performance, power, libraries and design rules for the actual PDK instead.
- Treating one company’s disclosure as a market benchmark. TSMC’s 15.0 million shipments, 17-million-plus capacity and 74% advanced-technology revenue share are TSMC-reported 2025 figures, not Samsung benchmarks.
- Turning “good yield” into a cross-vendor ranking. TSMC’s statement describes its own N2 process; no comparable Samsung yield figure is established here.
- Assuming a global footprint means every node is available everywhere. Verify the fab and country for the selected process, export controls and logistics.
- Ignoring package constraints. CoWoS, InFO, SoIC, COUPE and Samsung’s integrated packaging descriptions represent capabilities; package capacity, substrate and memory must be contracted for the product.
- Using total capacity instead of allocated capacity. A supplier’s headline number does not guarantee wafer starts during your ramp.
- Forgetting qualification and lifecycle needs. Industrial, automotive, medical and security products may need process-change controls, long-term supply and specialized reliability evidence.
Bottom line
TSMC offers the clearest public evidence of operating scale and a dated near-term advanced-node roadmap, while Samsung Foundry publicly emphasizes process breadth, specialty options, design enablement and integrated packaging. Neither public record proves a universal technical, economic or execution winner. Choose only after matching the exact PDK and IP, package flow, qualification requirements, production location, capacity commitment, yield assumptions and full commercial terms to the chip you intend to ship.
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