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Surface codes are the practical baseline for fault-tolerant quantum computers because they use local checks on a two-dimensional lattice, work with nearest-neighbor hardware, have fast, mature decoders, and can tolerate physical error rates often described as close to 1% in suitable models. Their weakness is scale: the number of physical qubits grows roughly with the square of code distance. Color codes retain topological locality but use different stabilizers and have more variable thresholds. Quantum LDPC codes can encode information far more efficiently, but usually require higher-degree or long-range connectivity and less mature decoding. Concatenated codes offer another trade-off, with recursive blocks whose performance depends heavily on the chosen code and circuit.
Why surface codes are still the default choice
A surface code is a two-dimensional topological stabilizer code. Data qubits are arranged on a lattice, while repeated measurements of local stabilizer operators reveal whether errors have occurred without directly measuring the encoded quantum state. The lattice has boundaries that define logical qubits and logical operators.
Its appeal is architectural as much as mathematical. Many superconducting and other solid-state processors naturally provide interactions between nearby qubits arranged in a plane. A surface-code check can therefore be built mostly from short-range gates rather than from arbitrary connections across the chip. The code also has a large body of decoder software, hardware-control experience and fault-tolerant circuit designs behind it.
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- High threshold in suitable models: widely cited surface-code studies place the threshold near 1%, although the exact value changes with the noise model, syndrome-extraction circuit, measurement errors, decoder and hardware graph.
- Fast decoding: minimum-weight matching and related methods can process the syndrome efficiently enough to be considered for real-time control.
- Engineering maturity: surface-code patches are the reference architecture against which many newer proposals are measured.
These advantages do not mean that a surface code is qubit-efficient. Increasing the distance from d to a larger value improves logical protection, but it also expands the patch in two dimensions. A distance-d patch needs approximately d2 data qubits for one logical qubit. Once syndrome-measurement qubits and the rest of the fault-tolerant layout are counted, the net encoding rate is about 1/(2d2). A distance-11 comparison cited in the 2024 Nature work had a net rate of roughly 1/241.
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That quadratic overhead becomes severe when a machine must host hundreds or thousands of logical qubits. The same Nature analysis concluded that scaling to 100 or more logical qubits would be prohibitively expensive if this surface-code overhead remains unchanged. Surface codes therefore win the near-term hardware-fit contest while leaving a major incentive to develop higher-rate alternatives.
How to interpret a quantum-code threshold
A threshold is the physical error rate below which increasing the code distance can reduce the logical error rate. It is not a universal score attached permanently to a code name. A reported threshold is meaningful only together with the assumptions used to obtain it.
- Noise model: depolarizing, biased, correlated, leakage or another error model can produce different results.
- Circuit model: a calculation may include only data-qubit errors or may also include faults in two-qubit gates, state preparation, measurement and idle periods.
- Syndrome extraction: the order and type of stabilizer-measurement operations affect hook errors and effective noise.
- Decoder: an idealized decoder can produce a different threshold from a constrained real-time decoder.
- Hardware graph: missing links, crosstalk, routing overhead and nonuniform error rates all change the result.
Some papers report a pseudo-threshold: the physical error rate at which one particular finite-size code performs as well as an unencoded qubit. A pseudo-threshold is useful for a near-term comparison, but it is not interchangeable with an asymptotic threshold obtained by studying how performance scales across many distances.
Surface, color, LDPC and concatenated codes compared
| Axis | Surface code | Color code | Quantum LDPC code | Concatenated code |
|---|---|---|---|---|
| Geometry | Two-dimensional local lattice with boundaries | Topological lattice with a different stabilizer pattern | Sparse checks; may require nonlocal links, multilayer routing or reconfigurable connectivity | Recursive blocks; connectivity depends on the block code and implementation |
| Representative threshold information | Often close to 1% in suitable 2D models | Highly protocol-dependent; one cited circuit-level study reported 0.082(3)% | Examples include about 0.7% for a BB-code comparison and 0.28% for a planarized LDPC proposal | Strongly code- and circuit-dependent |
| Encoding efficiency | Low rate, approximately 1/(2d²) after syndrome qubits are included | Usually low-rate topological scaling | Potentially constant-rate families with linear distance | Can be effective at small block sizes, but concatenation and gates add overhead |
| Decoding | Mature matching and related decoders | Specialized topological decoders | Active research, including belief propagation, ordered-statistics decoding and hybrids | Recursive or code-specific decoders |
| Hardware fit | Best match for nearest-neighbor two-dimensional hardware | Similar locality, with lattice-specific stabilizer measurements | Often needs higher degree, long-range connections, extra routing layers or flexible couplers | Varies with the gates needed by each block code |
| Implementation maturity | Most established baseline | Well studied but less dominant in hardware roadmaps | Rapidly advancing, with substantial engineering questions still open | Historically important and still useful in selected architectures |
The numbers in the threshold row are not a league table. They come from different studies and should not be ranked without matching their noise, circuit, decoder and connectivity assumptions.
Color codes: similar locality, different stabilizers
Color codes are another family of topological stabilizer codes. Instead of the surface code’s stabilizer arrangement, they use lattices whose faces or cells carry a color-based structure and whose checks can involve different numbers and patterns of qubits. The exact construction matters: two codes described as color codes can have different gate sets, lattice requirements and decoder behavior.
Their main attraction is that some color-code constructions support useful logical-gate operations more directly than a comparable surface-code layout. That can reduce the need for costly state-injection or code-switching procedures in a selected architecture. The benefit is conditional rather than universal; the stabilizer measurements and available transversal gates depend on the particular lattice and fault-tolerant protocol.
Threshold results illustrate the same caution. A circuit-level study by Landahl, Anderson and Rice reported 0.082(3)% for the color-code protocol and noise model it analyzed. The same body of comparisons cited 0.75–1.1% for comparable surface-code restrictions. Those figures do not establish that every color code has a lower threshold. They show that color-code performance is highly sensitive to the measurement circuit, decoder and lattice, and that a favorable logical-gate feature may come with a harder fault-tolerance budget.
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Color codes generally retain the surface code’s topological, local character, so they are more compatible with planar hardware than codes that require arbitrary long-range couplings. The price is less uniform hardware support and a smaller ecosystem of optimized decoders and control recipes.
Quantum LDPC codes: trading connectivity for encoding rate
Quantum low-density parity-check codes use sparse stabilizer checks, analogous in spirit to classical LDPC codes. The checks involve relatively few qubits even as the code grows, and newer constructions can have a constant encoding rate: the number of logical qubits grows proportionally with the number of physical qubits rather than remaining a small constant inside an ever-larger topological patch.
This addresses the surface code’s central weakness. A surface or color code usually encodes only a low constant number of logical qubits per patch, and its rate falls as distance increases. Quantum-LDPC families can offer substantially better asymptotic error-correction capability and much lower qubit overhead for a large logical processor.
The improvement is not free. Sparse checks may connect qubits that are far apart on a two-dimensional chip, or may require qubits with a higher coupling degree than today’s devices comfortably provide. Routing can require additional layers, movable couplers, photonic links or a three-dimensional package. Decoding is also less settled: belief propagation, ordered-statistics decoding and other algorithms are active areas of research, and their latency and behavior under degeneracy or correlated faults must be demonstrated in hardware.
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The BB-code comparison
The 2024 Nature BB-code study provides a concrete near-term comparison. Its reported BB-code examples had a threshold close to 0.7% under the study’s modeled conditions and showed roughly a tenfold reduction in encoding overhead relative to the surface-code comparison. A [[144, 12, 12]] BB code was assigned a net encoding rate of 1/24, whereas the distance-11 surface-code example had a net rate of about 1/241.
The connectivity requirement is materially different. In the cited BB-code layout, each physical qubit is coupled to six others, compared with the surface code’s local four-neighbor checks. That higher degree can make the code more efficient in qubits while making fabrication, calibration, crosstalk management and fault-tolerant scheduling harder.
The 0.7% figure is a study-specific comparison, not a universal BB-code threshold. Its meaning depends on the modeled physical noise, stabilizer-measurement circuit and decoder, just as the surface-code figure does.
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A planarized LDPC proposal
A separate 2022 Physical Review Letters proposal showed another point on the trade-off curve. Its planarized LDPC family reported a circuit-noise threshold of 0.28% and used 49 physical qubits per logical qubit in the stated construction. At a physical error rate of 10-4, the proposal reached a logical error rate of 10-15 with fourteen times fewer physical qubits than the surface-code comparison used in that work.
Planarization makes an LDPC graph easier to place on a chip, but it does not make it equivalent to a simple nearest-neighbor surface-code lattice. The proposal requires multilayer planar routing and long-range connections. Those resources may be practical in a package designed for them, but they impose different fabrication and control constraints from a flat square lattice.
Toric codes: the periodic-boundary relative of the surface code
The toric code uses the same broad topological idea as the surface code but closes the lattice with periodic boundaries, producing a torus in the mathematical model. Logical operators are noncontractible loops that wind around the torus. A surface-code patch instead uses boundaries, which are easier to represent on a finite chip and can be arranged to hold and move logical qubits.
Because the local stabilizer structure is closely related, toric and surface codes often have similar threshold behavior under comparable assumptions. A 2009 study reported a toric-code threshold of 7.8 × 10-3 (0.78%) with non-ideal syndrome extraction and found the surface-code threshold close to it. The precise value changes with the noise and decoder model.
The toric code is therefore best understood as a useful theoretical and benchmarking relative, not automatically as a more practical replacement for a finite surface-code patch. The boundary engineering of surface codes is usually more convenient for a processor with a physical edge.
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Concatenated codes protect each logical qubit by encoding it in a block, then encoding every qubit in that block again, sometimes through several levels. A small code can therefore be combined recursively to suppress errors without building one monolithic two-dimensional topological patch.
The approach can be efficient when a hardware platform naturally supports the block’s required gates, and it has a long history in fault-tolerant circuit design. However, its threshold, qubit overhead and decoding cost are strongly code-specific. A block code that looks efficient on paper may require difficult multi-qubit gates, long-range interactions or frequent code conversion. Conversely, a modest block code can be attractive when the device has all-to-all or highly connected interactions that make surface-code locality less valuable.
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Concatenation is therefore not a single competitor with one threshold number. It is an architecture strategy whose performance must be evaluated at the level of a complete encoded circuit.
Connectivity is the hardware dividing line
The most important practical difference among these families is often the hardware graph rather than the algebra of the code.
Nearest-neighbor two-dimensional hardware
A surface-code patch maps naturally to a square grid in which a qubit interacts with a small number of neighbors. This minimizes routing and makes repeated stabilizer cycles predictable. Color codes can also be local, but their lattice-specific checks may need different schedules or qubit degrees.
Higher-degree local hardware
Some LDPC layouts can remain physically compact if each qubit has more couplers. The BB-code example’s six-neighbor connectivity illustrates the exchange: fewer qubits for the same logical capacity, but more demanding wiring and calibration than four-neighbor surface-code checks.
Long-range or multilayer links
Other LDPC constructions use connections that are not available in a single planar layer. Multilayer routing, vertical interconnects, tunable couplers, modular links or reconfigurable photonic connections can supply them. These options may unlock high-rate codes, but they add loss channels, control complexity and new failure modes that must be included in the threshold model.
Connectivity for concatenated blocks
Concatenated-code implementations vary most widely. Some blocks need only local gates; others rely on interactions among distant members of the block. The right choice depends on whether the processor is optimized for a grid, a small-world graph, a modular network or a more highly connected architecture.
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Decoding and control-system consequences
Every code produces a stream of syndrome measurements rather than a direct report of the logical state. A decoder must infer the most likely error pattern and tell the control system which correction, frame update or lattice operation to apply.
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Color-code decoders are specialized to their lattice and syndrome structure. They can be efficient, but the available software and hardware acceleration are less standardized than for surface codes.
Quantum-LDPC decoding is a major research and engineering challenge. Belief propagation can exploit sparse checks, while ordered-statistics decoding and hybrid methods can address cases where basic message passing struggles. A decoder must also cope with measurement faults, degeneracy and the latency of a high-throughput syndrome stream. A code that saves physical qubits but cannot be decoded within the hardware cycle may not deliver a useful logical machine.
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There is no defensible universal ranking. In the supplied comparisons, a surface code is often near 1% in suitable two-dimensional models; a toric-code study found 0.78% under non-ideal syndrome extraction; the cited color-code circuit study found 0.082(3)%; the BB-code comparison reported about 0.7%; and the planarized LDPC proposal reported 0.28% under circuit noise.
Those values were obtained with different assumptions and cannot be sorted as if they were measurements from one experiment. A lower threshold can still accompany a better architecture if the code uses far fewer qubits or reaches the required logical error rate at a practical physical error rate. Conversely, a high threshold is not enough if the hardware cannot supply the connectivity or the decoder cannot keep up.
When comparing two papers, put the following on the same line before comparing percentages: physical error model, whether measurement and gate faults are included, syndrome-extraction schedule, code distance or block size, decoder type, connectivity graph and whether the number is an asymptotic threshold or a finite-size pseudo-threshold.
How to choose a code for an architecture
- Start with the hardware graph. If the processor is a regular two-dimensional nearest-neighbor array, surface or color codes avoid a large routing penalty. If the device already supports high-degree or long-range links, an LDPC construction may justify its extra control complexity.
- Set the logical workload. A few logical qubits may tolerate surface-code overhead. A machine targeting 100 or more logical qubits should quantify the quadratic patch cost early rather than assuming that distance can be increased indefinitely.
- Specify the target logical error rate. A threshold alone does not say how many physical qubits are required. Estimate the distance, number of syndrome cycles and decoder latency needed for the actual algorithm.
- Model the complete syndrome circuit. Include two-qubit gates, measurement, reset, leakage, idle errors and correlated faults. Do not use a data-only threshold to size a circuit that will be dominated by measurement errors.
- Budget decoder hardware. Compare memory bandwidth, latency and power as well as algorithmic accuracy. A high-rate code is useful only if its syndrome stream can be processed in time.
- Evaluate logical-gate costs. Color-code constructions may offer useful transversal operations; surface-code systems may rely on lattice surgery, code deformation or injected resource states. Include those operations in the architecture-level qubit and time budget.
- Plan for calibration and yield. Higher-degree and multilayer connections increase the number of couplers and possible failure modes. A code that is optimal for identical simulated components may be less robust when fabrication variation is included.
The practical trade-off in one view
- Choose a surface code when locality, decoder maturity and compatibility with a two-dimensional processor are the primary constraints.
- Consider a color code when its logical-gate properties fit the workload and the hardware can implement its lattice-specific checks with acceptable errors.
- Investigate a quantum LDPC code when physical-qubit efficiency is critical and the platform can provide higher-degree, long-range or multilayer connectivity plus a capable decoder.
- Use a concatenated code when the device’s native connectivity and gate set make recursive blocks cheaper or simpler than a large topological patch.
Surface codes remain the baseline not because they minimize every resource, but because they balance threshold, locality, decoding and hardware readiness unusually well. Other codes become compelling when a processor can pay for their harder connectivity or decoding in exchange for much better encoding efficiency. The meaningful comparison is therefore an end-to-end architecture result, not a single threshold percentage.
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