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SK hynix is developing the Hynix Transaction Processing Unit (H-TPU), a very small programmable processor for repetitive SSD-controller work. The design is intended to let more than 100 specialized cores handle routine I/O tasks while a conventional Arm CPU concentrates on recovery, exceptions and storage policy. It is an announced architecture, not a shipping SSD product, so its eventual effect on drive speed and power remains unproven.
What SK hynix announced
At the ISOCC 2026 conference, SK hynix vice president of SoC design Koo In-jae described H-TPU as an in-house core for the transaction-heavy parts of a flash controller. Tom’s Hardware and TheElec report that each H-TPU uses a four-stage, in-order pipeline. Its intended jobs include processing read and write commands, handling metadata and controlling buffers.
The design responds to a widening imbalance in modern storage. PCIe bandwidth doubles with each generation, but a controller’s general-purpose CPU cannot simply keep increasing clock speed and control complexity: power and die-area budgets limit that approach. Offloading predictable work to many small cores is SK hynix’s way of scaling control capacity without making the main CPU disproportionately larger or hotter.
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How the controller would divide the work
H-TPUs handle repetitive transactions
H-TPUs are meant to run specialized routines in parallel clusters. Read and write command processing, metadata manipulation and buffer movement are regular enough to be distributed across numerous small programmable cores. SK hynix’s described architecture contains more than 100 H-TPUs, according to TheElec’s report.
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The Arm CPU keeps unpredictable work
The conventional Arm processor would remain responsible for error recovery, exception handling and storage-policy decisions. Those paths are less predictable and often require broader software context, making them a poor fit for a tiny in-order core. Keeping them on the main CPU also preserves a flexible control path when NAND behavior, firmware state or a failed operation does not match the normal flow.
Fixed circuits could automate the most regular paths
SK hynix’s next step is described as “hardware automation.” Command processing, address lookup and buffer copies could move into fixed-function circuits, while H-TPUs retain programmable control for work that changes more often or cannot be expressed efficiently in dedicated logic. That creates a three-level division: fixed hardware for the most deterministic operations, H-TPUs for programmable repetitive work and the Arm CPU for exceptions and policy.
What the published power and area figures mean
SK hynix’s reported comparisons are architectural, per-core figures rather than measurements of a complete SSD.
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| Measure | Reported H-TPU figure | How to interpret it |
|---|---|---|
| Power per core | About 2.5% of a general-purpose CPU core’s power | A per-core comparison attributed to SK hynix in 2026 reports; it does not predict total drive power. |
| Area per core | About 4% of a general-purpose CPU core’s area | A per-core die-area comparison, not the area of a finished controller with more than 100 cores. |
| Scale in the described design | More than 100 H-TPUs | The reported controller architecture; it is not a confirmed production configuration. |
Those figures suggest why many small cores could be attractive, but they do not establish lower SSD watts, higher IOPS, lower latency or a particular controller die size. Interconnects, memory, firmware, NAND channels and the main CPU all contribute to a real controller’s power and area.
Is H-TPU an AI accelerator?
No. H-TPU is described as a programmable transaction-processing core, not a matrix engine or neural-network accelerator. Its immediate purpose is storage control: issuing and completing I/O, looking up addresses, managing metadata and moving data through buffers.
It is connected to SK hynix’s broader Storage Next and AIN P work on fine-grained access to storage for AI systems. In that context, efficient command handling can help keep flash feeding an inference workload, but that does not turn H-TPU itself into an AI compute unit.
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How it compares with other controller offload approaches
Small task-specific processors are not new in storage. Tom’s Hardware cites Phison’s CoXProcessor and controller designs that combine Arm Cortex-R cores with additional task-oriented resources. The reported distinction for H-TPU is its scale and the dedicated compiler and development tools intended to make a large population of programmable small cores practical.
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|---|---|---|
| Conventional multi-core Arm controller | Broad software compatibility and flexible exception handling | More power and area as transaction rates rise; limited scaling under a fixed budget. |
| H-TPU cluster | Many low-cost programmable workers for predictable I/O routines | Requires a compiler, toolchain and firmware partitioning that can keep the cores busy without adding coordination overhead. |
| Fixed-function automation | Very efficient execution of stable command, lookup and copy paths | Less adaptable when protocols, NAND behavior or algorithms change. |
| Mixed offload designs | Combine general-purpose Arm cores with specialized processing resources | Results depend on workload balance, software maturity and the implementation; no H-TPU production benchmark is available. |
Useful comparison measurements would include power per I/O operation, controller die area, toolchain maturity, exception-handling flexibility, predictable latency and small-block IOPS. None of those has been independently demonstrated for an H-TPU-equipped product.
Could H-TPU make SSDs faster or more efficient?
Potentially, but only indirectly. If routine transactions consume less controller power and leave the Arm CPU available for recovery and policy tasks, a controller could sustain more concurrent work within the same thermal envelope. Specialized workers may also make latency more predictable when many small requests arrive at once.
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Those are architectural possibilities, not measured outcomes. NAND media, channel count, DRAM or SRAM, firmware scheduling, PCIe implementation and host workload can dominate end-to-end performance. The reported per-core percentages cannot be converted into a percentage improvement for an entire SSD.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.When could H-TPU SSDs ship?
SK hynix says it plans to apply the architecture across NAND products, including next-generation enterprise SSD controllers. Its Storage Next/AIN P efforts and the company’s interest in high-bandwidth flash (HBF) place H-TPU in an AI-storage roadmap: HBF relies on buffer management and prefetching to hide NAND latency behind compute.
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SK hynix’s official OCP 2025 roadmap targeted samples of next-generation NAND and controller solutions by the end of 2026. That roadmap does not name an H-TPU retail model, and no researched source provides a firm launch date for an H-TPU enterprise SSD.
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- No production H-TPU SSD has been identified.
- No independent benchmark of throughput, latency, IOPS or controller power has been published.
- A sampling target for next-generation solutions is not a promise that a retail drive using H-TPU will be available on that date.
What enterprise buyers should watch
Until a controller or SSD is announced, H-TPU is best treated as an architectural development rather than a product specification. A meaningful evaluation will require a named drive, firmware version, NAND configuration and workload results. Buyers should look for power per operation, sustained small-block IOPS, tail latency under mixed reads and writes, recovery behavior during NAND errors and evidence that SK hynix’s compiler and firmware tools are mature enough for long-term support.
The central idea is clear: use tiny programmable workers for the predictable flood of SSD transactions, reserve the Arm CPU for decisions that need flexibility and eventually hard-wire the most stable paths. Whether that division produces a faster or lower-power drive will be known only when SK hynix ships hardware and publishes comparable measurements.
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