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Silicon spin qubits offer the smaller, potentially more semiconductor-compatible building block; superconducting qubits offer the more mature large-system record. That is the useful answer, but it is not a universal winner. Silicon’s submicrometre devices and possible CMOS/VLSI manufacturing route could eventually support much denser arrays, while superconducting processors have already demonstrated larger coupled systems and a comparatively developed control ecosystem. Both still face major engineering limits in wiring, cryogenic operation, device variation, and fault-tolerant scaling.
The figures below come from different devices, dates, and test conditions. They should be read as evidence of platform direction, not as a single head-to-head benchmark.
What the two qubit architectures are
Silicon spin qubits
A silicon spin qubit stores information in the spin state of an electron or, in some implementations, a nucleus confined in a semiconductor structure. Gate electrodes form and tune quantum dots, and the device’s small dimensions allow several dots to be placed close together. Electric-dipole spin resonance or related spin-resonance techniques drive individual qubits, while exchange interactions between neighbouring confined particles provide an important two-qubit coupling mechanism.
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Spin is comparatively insensitive to electric fields, which can support long coherence under suitable conditions. The trade-off is that the spin must be controlled indirectly through electric gates, magnetic fields or micromagnets, and precisely tuned semiconductor interfaces. Noise in charge, materials, interfaces and control electronics can still disturb the operation.
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Superconducting qubits
Superconducting qubits are lithographically patterned circuits containing Josephson junctions and resonators. They operate as engineered artificial atoms. Microwave pulses manipulate the circuit states, and microwave measurement chains read them out. Couplers or resonator-mediated interactions connect neighbouring qubits.
The platform uses fabrication methods related to established thin-film and semiconductor processing, but its circuits are physically much larger than quantum dots and must be cooled to millikelvin temperatures. Larger physical dimensions make routing and microwave control more accessible at small scale, while the refrigerator, wiring and electromagnetic environment become increasingly difficult as the system grows.
What has actually been demonstrated at scale?
The clearest maturity difference comes from dated system-level evidence. An imec comparison published in 2023 described superconducting circuits as arguably the most developed qubit platform and cited systems with more than one hundred coupled qubits. The same account discussed silicon spin qubits as substantially smaller but more difficult to control. That is a historical comparison from 2023, not a claim that every current superconducting processor has the same capability or that silicon development has stopped.
Silicon’s strongest evidence is currently at the device, wafer and integration levels rather than in a demonstrated million-qubit processor. A Nature study published in May 2024 used a cryogenic 300-mm wafer-probing process to test hundreds of industry-manufactured spin-qubit devices at 1.6 K. The work reported low disorder after process optimization, while identifying process variation and yield as continuing scale-up concerns.
| Evidence or metric | Silicon spin qubits | Superconducting qubits | How to interpret it |
|---|---|---|---|
| Physical device size | Approximately 100 nm for silicon quantum-dot spin qubits in the 2024 Nature study | Not stated in the cited comparison | Different device generations and definitions; not a processor-area benchmark |
| Footprint cited in manufacturing review | Below 1 µm², in the 2025 European Physical Journal A review | Not stated | Describes the potential spin-device footprint, not a complete system including wiring and control |
| Wafer-scale testing | 300-mm wafer; hundreds of industry-manufactured devices tested at 1.6 K in 2024 | Not stated in the supplied sources | Evidence for high-volume characterization, not a full-processor yield demonstration |
| Largest coupled-system figure cited | The 2024 paper discusses integrated arrays reaching six quantum dots, with larger one- and two-dimensional demonstrations also reported | More than one hundred coupled qubits, cited by imec in 2023 | Source dates and system definitions differ |
| Operating temperature evidence | Above 1 K demonstrated in a particular 2024 experiment | Millikelvin operation is typical for the platform | An experiment above 1 K is not evidence of commercial operation at that temperature |
| Coherence figure | No single value established by the cited sources | Up to several hundred microseconds in laboratory environments, as reported by imec in 2023 | Conditions, qubit designs and measurement definitions are not matched |
The silicon array numbers in the table describe the scope of the 2024 wafer-probing paper, not an inventory of every device available in 2026. Likewise, the superconducting count and coherence range are the figures in imec’s 2023 comparison and should be dated whenever they are quoted.
Why silicon looks attractive for dense scaling
Very small active devices
The 2025 European Physical Journal A manufacturing review describes silicon spin-qubit footprints below 1 µm². The 2024 Nature wafer study describes individual silicon quantum-dot spin qubits as approximately 100 nm in size. Such dimensions create the possibility of placing many physical qubits in the area occupied by a much smaller number of superconducting circuits.
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Small active devices do not automatically produce a small quantum computer. Control gates, charge sensors, microwave or radio-frequency lines, amplifiers, shielding and routing can dominate the area. A dense array is useful only if each qubit can be addressed, measured and calibrated without unacceptable crosstalk or heat.
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Silicon fabrication can reuse parts of the ecosystem developed for CMOS and VLSI: large wafers, lithography, thin-film deposition, metrology and automated process control. The 2025 review presents CMOS/VLSI compatibility as a possible scale-up route, not as proof that a million-qubit processor can be manufactured today.
Quantum devices impose additional requirements. Materials and interfaces must support low-disorder operation; dimensions must be controlled at the level required for single-charge physics; fabrication must work at cryogenic temperatures; and the process must deliver a useful distribution of qubit frequencies, tunnel barriers, charge sensors and couplers. The review explicitly warns that adopting silicon technology alone does not solve these problems.
Wafer-level evidence and its limits
The 300-mm cryogenic wafer-probing study is important because it moves testing beyond a few hand-selected laboratory devices. Researchers measured hundreds of industry-manufactured devices at 1.6 K and observed low disorder after process optimization. This enables statistical analysis of variation and a more realistic view of manufacturing.
It is not, however, a complete processor-yield study. A wafer can contain many individually functioning devices while still failing to produce a large, connected, calibrated and uniformly controllable processor. Yield must eventually include the entire stack: qubit formation, couplers, sensors, wiring, cryogenic electronics, packaging and software calibration.
Why superconducting systems remain more mature
Larger demonstrated coupled arrays
Superconducting circuits have had a longer period of investment in multi-qubit integration, calibration software, microwave packaging and error-characterization methods. Imec’s 2023 comparison cited more than one hundred coupled qubits and called the platform arguably the most developed. That record gives superconducting teams a larger base for studying system-level effects such as crosstalk, calibration drift and repeated two-qubit operation.
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Maturity does not remove the scaling problem. A larger coupled array is not the same as a fault-tolerant machine, and the cited sources do not establish a universal superconducting processor size, error-correction threshold achievement or production yield for 2026.
More accessible control at small scale
Microwave pulses and resonator readout provide a comparatively direct control model. Engineers can characterize pulse amplitude, frequency, phase and timing using established radio-frequency instrumentation. The architecture is still demanding: microwave loss, impedance control, frequency crowding, crosstalk, packaging and calibration all become harder as qubit counts rise.
Superconducting qubits are also sensitive to electromagnetic noise and heat. Their larger physical structures ease some local wiring tasks but increase the burden of delivering many high-frequency signals into a refrigerator without warming the cold stages.
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Silicon control chain
In a spin array, gate electrodes define quantum dots and tune tunnel barriers and energy levels. Spin-resonance or electrically driven spin-resonance signals manipulate states, while exchange coupling supplies a key route to two-qubit operations. Charge sensors or related detectors convert the spin state into a measurable electrical signal.
The difficulty is density. Individual dots must be connected to one another and to classical electronics, yet the devices are so small that routing can overwhelm the nominal qubit area. Control voltages can shift neighbouring dots, and variations in tunnel barriers or sensor response can require individual calibration. The Reviews of Modern Physics survey on semiconductor spin qubits identifies exchange interactions as central to single- and two-qubit control and discusses noise and alternative implementations.
Superconducting control chain
Early superconducting processors commonly used at least one control line per qubit from room temperature to the refrigerator’s cold stage, according to the imec comparison. Every line occupies connector, cable and filtering capacity and carries heat toward cold stages. Refrigerator input/output and wire heat load therefore become central limits for larger systems.
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Cryo-CMOS multiplexing could reduce the number of lines routed from room temperature by placing some control and switching functions near the qubits. It introduces its own power dissipation, noise coupling and fabrication challenges. The same imec account highlights electromagnetic-noise sensitivity and heat as continuing concerns.
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Silicon operation above 1 K
A Nature experiment published in March 2024 demonstrated high-fidelity spin-qubit operation and algorithmic initialization above 1 K. Operating at a higher temperature could make it easier to place classical electronics near the quantum device, potentially shortening interconnects and reducing the number of signals entering the coldest refrigerator stage.
The result is a specific experimental demonstration, not evidence that commercial spin processors operate above 1 K. The authors state that control and state-preparation/readout errors still need improvement and that engineering a fault-tolerant million-qubit system remains formidable.
Millikelvin electronics
A Nature paper whose version of record appeared in June 2025 reported control of MOS-style silicon spin qubits with a heterogeneously integrated cryo-CMOS chip operating at millikelvin temperatures. This demonstrates that control electronics can be integrated close to the qubits. It does not show that wiring has ceased to be a system-level bottleneck: the paper’s introduction identifies the high density of connections between qubits and external control/readout hardware as a scaling barrier.
For superconducting systems, millikelvin operation is intrinsic to the circuit technology. Any local electronics must dissipate little enough power to preserve the refrigerator’s temperature margin, and microwave lines must be filtered and attenuated without losing signal integrity.
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| Metric | Silicon spin qubits | Superconducting qubits | Comparison caution |
|---|---|---|---|
| Single-qubit gate fidelity | Not stated as a universal value in the supplied sources | Not stated as a universal value | Fidelity depends on device, pulse sequence, calibration and measurement protocol |
| Two-qubit gate fidelity | Not stated as a universal value | Not stated as a universal value | Coupler design, leakage and crosstalk must be specified |
| Readout fidelity and speed | Not stated | Not stated | Sensor type, integration time and assignment-error definition matter |
| Coherence | Spin’s relative electric-field insensitivity can support long coherence; no single number is established here | Up to several hundred microseconds in laboratory environments in imec’s 2023 account | Different noise environments and operating temperatures prevent a direct ranking |
| Gate speed | Not stated | Not stated | Fast gates are useful only if errors and heating remain controlled |
| Connectivity | Exchange coupling is naturally local; larger connectivity requires additional couplers or movement protocols | Typically local couplers or resonator links; architecture-specific | No connectivity topology is specified well enough for a universal winner |
A platform can lead on one metric and lose on another. Longer coherence does not compensate for slow or inaccurate readout; fast gates do not help if calibration drifts; and a high device count does not establish fault-tolerant logical qubits.
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Manufacturing variation, yield and packaging
Silicon’s industrial heritage is an opportunity rather than a guarantee. Quantum-dot operation depends on microscopic disorder, interface quality, dopant or electrostatic profiles, tunnel-barrier dimensions and sensor characteristics. A process that produces acceptable classical transistors may still produce a broad spread of quantum-dot behaviour.
The 2024 wafer study specifically frames process variation and yield as historical challenges for spin-qubit results. Its low-disorder measurements after optimization are encouraging, but they do not establish the yield of a complete processor with all qubits connected and operational. Statistical process control, redundancy, automated tuning and packaging will be necessary before wafer throughput translates into useful quantum volume.
Superconducting fabrication also requires tight control of junction parameters, film uniformity, interfaces and resonator frequencies. Larger systems expose frequency collisions and packaging defects that may not appear in a small prototype. Industrially compatible fabrication and cryogenic control remain active scale-up subjects for that platform as well.
Connectivity and error-correction implications
Spin qubits are usually coupled to nearby neighbours through exchange interactions. Local connectivity keeps interactions physically compact but can make long-range operations expensive. Additional routing, shuttling, mediator dots or resonators may increase connectivity at the cost of more control parameters and more opportunities for error.
Superconducting architectures also commonly begin with local couplers or resonator links. Their larger physical footprint can make some routing easier, but a two-dimensional chip still requires careful placement, frequency allocation and microwave isolation. Moving from a physical array to a fault-tolerant machine requires repeated high-fidelity gates, reliable measurement, fast reset and an error-correction scheme whose overhead is included in the system design.
The supplied sources do not establish a completed, directly comparable fault-tolerant demonstration for either platform. Claims about a future million-qubit machine should therefore be treated as engineering targets, not demonstrated capability.
How to choose a platform for a specific goal
Choose silicon spin qubits when the priority is density and semiconductor integration
- You need the smallest plausible physical qubit and see value in a potential CMOS/VLSI manufacturing path.
- You are prepared to develop cryogenic control, calibration and yield-screening methods alongside the qubit process.
- Your roadmap can tolerate today’s smaller demonstrated arrays while process variation and interconnect methods mature.
- You want to investigate operation above 1 K or cryo-CMOS integration as a way to reduce room-temperature wiring.
Choose superconducting qubits when the priority is near-term system maturity
- You need a platform with a comparatively developed multi-qubit control and calibration ecosystem.
- Your program benefits from the larger coupled-system demonstrations cited by imec in 2023.
- You can support millikelvin refrigeration, microwave instrumentation, filtering and the associated heat budget.
- You are prepared to engineer around electromagnetic sensitivity, line count and frequency crowding.
Use a matched scorecard, not a slogan
- Define the target logical workload and required logical error rate before choosing a physical qubit.
- Specify the device generation, array size, temperature and measurement protocol for every performance number.
- Measure two-qubit fidelity, readout assignment error, reset time and calibration stability on the same system.
- Include wiring, amplifiers, cryo-CMOS power, packaging and refrigerator capacity in the area and energy model.
- Estimate yield for a connected processor, not just the percentage of individually functioning test devices.
- Track the engineering path from today’s array to error-corrected logical qubits, including routing and decoding overhead.
Bottom line
Silicon spin qubits have the stronger geometric and semiconductor-manufacturing argument: devices can be about 100 nm in a reported implementation, a 2025 review places the spin-device footprint below 1 µm², and wafer-scale cryogenic testing has reached hundreds of devices on a 300-mm wafer. Those results show a plausible route to dense integration, not a demonstrated million-qubit processor.
Superconducting qubits have the stronger maturity argument. Imec’s 2023 comparison cited more than one hundred coupled qubits and laboratory coherence times up to several hundred microseconds, while also documenting the platform’s wiring, heat and electromagnetic-noise limits. Silicon faces its own control and yield barriers, even when its active devices are much smaller.
The defensible conclusion is conditional: superconducting circuits currently provide the more developed large-system base, while silicon spin qubits offer a compelling long-term scaling hypothesis. The better choice depends on whether your dominant constraint is demonstrated system maturity or the prospect of dense, semiconductor-integrated hardware.
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