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Short answer: choose silicon carbide (SiC) first when your converter must block high voltage and process substantial power, as in traction inverters, high-power solar, fast charging and grid equipment. Choose gallium nitride (GaN) when high switching frequency and power density can make the converter smaller, as in compact AC adapters, isolated DC/DC stages and point-of-load supplies. The boundary is not fixed: device ratings, topology, thermal path, gate drive, layout, reliability targets and total system cost decide the practical choice. Many modern systems use SiC, GaN and silicon in different stages rather than selecting one material for the entire product.
What SiC and GaN change compared with silicon
SiC and GaN are wide-bandgap semiconductor materials. Compared with conventional silicon MOSFETs, their material properties can support lower switching losses, higher temperature capability and faster switching when the device, package and circuit are designed appropriately. Those benefits can increase efficiency or allow smaller inductors, transformers, capacitors, heat sinks and enclosures. They do not remove the need to evaluate the complete converter.
A material is not a finished switch. The voltage rating, on-resistance, gate-charge behavior, output capacitance, reverse-conduction path, package inductance, thermal resistance and gate-driver requirements come from a particular device and process. A well-designed silicon switch can outperform a poorly applied wide-bandgap device, while a carefully optimized SiC or GaN stage can reduce losses and passive-component volume enough to justify a higher semiconductor price.
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Start with the converter stage, not the material label
Define the electrical and mechanical problem before comparing part numbers. At minimum, document the following:
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- Bus and transient voltage: include nominal, maximum, surge and switching overshoot. Select a blocking-voltage margin appropriate for the topology and applicable safety rules.
- Current and power: specify continuous, RMS, peak and overload current, plus duty cycle and ambient-temperature range.
- Topology: a hard-switched boost, phase-shifted full bridge, totem-pole PFC, LLC resonant converter and motor inverter impose different voltage and commutation stresses.
- Switching target: state the intended frequency, allowable transition time, dead time and soft-switching conditions.
- Isolation and safety: identify isolation voltage, creepage, clearance, common-mode-current limits and regulatory requirements.
- Thermal envelope: set the allowed junction, case, heat-sink and enclosure temperatures and the available cooling method.
- Manufacturing constraints: include production volume, available assembly processes, inspection capability, field-reliability targets and component availability.
Only after those requirements are fixed should you compare datasheet loss curves, package options and system cost. A device that looks attractive at one operating point may be unsuitable at the actual line voltage, switching frequency or transient condition.
Voltage and power: the first screening decision
Texas Instruments’ fourth-quarter 2020 overview characterizes SiC devices as reaching 1,200 V with high current-carrying capability. It associates them with traction inverters, high-power solar farms and large three-phase grid converters. The same article describes GaN FETs as typically 600 V and associates them with consumer, server, telecom and industrial power supplies, servo drives, grid converters, electric-vehicle onboard chargers and DC/DC converters. These are dated, source-specific application descriptions, not universal limits for every current device.
Current device architecture matters. Onsemi’s GaN technology page describes lateral GaN commonly from approximately 30 V to 650 V, with some designs approaching 900 V. It describes vertical GaN as typically above 900 V and beyond 1,200 V. Those ranges cannot simply be merged with the older “typically 600-V” description: they refer to different architectures and dates. For a real design, the individual device datasheet and qualification documentation govern.
| Screening question | What the published examples suggest | Design interpretation |
|---|---|---|
| High-voltage, high-current front end | TI’s 2020 overview highlights SiC up to 1,200 V and high current. | Start the evaluation with SiC devices and modules, then verify voltage margin, short-circuit behavior and thermal performance. |
| Compact sub-1-kV switching stage | TI identifies many GaN FETs as typically 600 V; onsemi lists lateral GaN to about 650 V and some designs near 900 V. | GaN is a candidate when frequency and density matter, but check the exact rating, isolation arrangement and transient margin. |
| Above-900-V GaN architecture | Onsemi describes vertical GaN as typically above 900 V and beyond 1,200 V. | Do not assume that a high-voltage GaN option has the same gate-drive, packaging or availability as a lateral device; evaluate the specific platform. |
| Mixed-voltage product | Both vendors describe overlap and stage-by-stage use of technologies. | Use the most suitable switch family in each stage instead of forcing one material across the whole power tree. |
For a 400-V or 800-V DC link, calculate overshoot from package and layout inductance before choosing a nominal rating. For a three-phase inverter or PFC front end, also check fault energy, short-circuit withstand time and the protection system. A nominal voltage number alone is not a safe selection method.
When GaN is the better fit
High frequency that reduces passive size
GaN is most compelling when higher switching frequency produces a system-level benefit. Raising frequency can reduce the required inductance or transformer size, shorten transient response and increase power density. The gain appears only if switching losses, gate-drive losses, electromagnetic interference and thermal dissipation remain controlled.
Compact adapters and isolated DC/DC converters
Consumer and enterprise adapters, intermediate-bus converters, isolated DC/DC stages and point-of-load regulators often have a strong incentive to reduce volume and weight. TI names USB Type-C adapters as an example of a GaN application. That does not mean every USB-C charger uses GaN; the technology is simply one option for meeting a compact, efficient design target.
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Motor, servo and actuation stages
Onsemi identifies motor drives and actuation among potential GaN applications. These stages may benefit from fast current control and small magnetic components, but the designer must verify dv/dt tolerance, motor insulation stress, common-mode current, bearing-current mitigation and the controller’s timing resolution.
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- Very short, low-inductance power and gate-drive loops.
- A gate driver matched to the device’s recommended voltage, current and timing.
- Careful control of turn-on and turn-off speed to limit ringing and electromagnetic interference.
- Accurate dead-time management, especially in half bridges where reverse conduction can add loss.
- Layout and measurement methods capable of resolving fast voltage and current edges without introducing probe artifacts.
GaN should therefore be selected as a switching system, not as a drop-in replacement for a silicon MOSFET with the same footprint and gate resistor.
When SiC is the better fit
High-voltage front ends and energy infrastructure
SiC is often the starting point for high-voltage, high-power conversion. Onsemi lists SiC MOSFETs and modules for DC fast charging, energy storage, solar inverters and uninterruptible power supplies. These product categories span many ratings and topologies, so the application label does not replace checking the individual electrical and thermal specifications.
Traction and large inverters
Traction inverters and industrial motor drives must handle high bus voltage, substantial current, repetitive overloads and demanding thermal cycles. SiC modules can provide a practical combination of blocking voltage, current capability and switching performance. The final choice still depends on modulation strategy, switching frequency, cooling plate, fault protection and required lifetime.
Faster SiC operation is possible
SiC is not limited to low-frequency switching. An onsemi article gives SiC examples in a totem-pole power-factor-correction stage at 100 kHz and in a soft-switching LLC converter at 200–300 kHz. Those are vendor examples under particular circuit and device conditions, not universal operating prescriptions. Resonant operation, zero-voltage switching and an optimized gate drive can make high-frequency SiC practical, while a hard-switched circuit may be limited by losses and EMI.
Switching frequency and topology determine the trade-off
| Topology or stage | Why GaN may help | Why SiC may help | Checks that decide the result |
|---|---|---|---|
| Totem-pole PFC | Fast transitions can reduce commutation loss and enable a compact magnetic design. | Higher-voltage and higher-power implementations may favor SiC switches or diodes. | Line voltage, dead time, reverse conduction, common-mode EMI, transient overshoot and control timing. |
| LLC resonant converter | High frequency can shrink the transformer and resonant components. | SiC can operate in higher-power versions; soft switching reduces turn-on loss. | Resonant range, magnetizing current, zero-voltage-switching margin, light-load behavior and thermal path. |
| Hard-switched boost or buck | Low charge and fast switching can improve transient response and density. | Higher-voltage margin and robust power handling can be decisive. | Turn-on and turn-off energy, output-capacitance loss, diode or reverse-conduction behavior and snubber design. |
| Motor inverter | Fast control edges and smaller filters may be useful at moderate voltage. | High-voltage traction and industrial power levels commonly point toward SiC. | dv/dt at the motor terminals, insulation stress, short-circuit protection, switching frequency and cooling. |
| Point-of-load regulator | High frequency can reduce inductance and improve response in a small footprint. | SiC is usually considered only when voltage or power moves beyond the practical GaN range. | Current ripple, control-loop bandwidth, package parasitics and load-transient requirements. |
Frequency alone is not a selection rule. Compare total switching loss, conduction loss and passive loss at the actual duty cycle and temperature. A lower-loss switch at 100 kHz can produce a smaller system than a theoretically faster switch operated at a frequency that overwhelms the thermal design.
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Thermal design and packaging: evaluate the whole path
Wide-bandgap devices can reduce loss, but the junction temperature is determined by the complete path from silicon or compound-semiconductor die through package, interface material, heat spreader, heat sink and airflow or coolant. Review junction-to-case and case-to-sink thermal resistance, transient thermal impedance, maximum junction temperature, mounting pressure and the temperature dependence of on-resistance.
Fast edges also make package inductance electrically significant. Common-source inductance can alter the effective gate voltage; power-loop inductance can create overshoot; mutual coupling can produce false turn-on in the opposite switch. Kelvin-source connections, laminated bus bars, integrated drivers and carefully placed decoupling capacitors may be more important than a small difference in room-temperature on-resistance.
- Build a loss model that includes conduction, turn-on, turn-off, output-capacitance, reverse-conduction and gate-drive losses.
- Run the model at hot and cold corners, minimum and maximum input voltage, light and full load, and the intended switching frequency.
- Measure the thermal interface and airflow assumptions on the actual mechanical assembly.
- Check whether switching transitions create EMI that forces a lower frequency or larger filter, erasing the expected density benefit.
Do not convert a material-level claim such as “lower loss” into a guarantee of a lower system temperature. A smaller heat sink may be possible, but only after the complete operating envelope is demonstrated.
Gate drive, protection and layout differences
Gate-drive requirements
GaN and SiC gates have different voltage ranges, charge characteristics and tolerance for overvoltage. Use the manufacturer’s recommended driver supply, maximum negative or positive gate voltage and turn-on/turn-off current. A driver chosen only by peak-current rating may have excessive propagation delay, poor common-mode transient immunity or unsuitable isolation behavior.
Protection
Design desaturation, overcurrent, overvoltage and short-circuit protection around the device’s specified response time. SiC short-circuit withstand capability varies by device and operating condition. GaN protection must account for very fast fault development and the absence of a conventional body diode in many structures. Coordinate the protection threshold with stray inductance so that normal switching spikes do not create nuisance trips.
Layout and measurement
Place high-frequency bypass capacitors directly across the switching loop, minimize gate-loop area, separate power and control returns, and provide a defined path for common-mode currents. Use differential probes and low-inductance current measurement; a long oscilloscope ground lead can make an acceptable waveform appear to have ringing that is not present, or hide a real overshoot.
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System cost: compare the bill of materials, not the transistor price
Onsemi’s 2023 silicon-based 30 kW example says 90% of the overall cost is associated with inductors and capacitors—60% and 30%, respectively—while semiconductor devices represent 10% of the bill of materials. The same passage presents a case in which replacing silicon MOSFETs with SiC switches permits a 75% reduction in capacitance and inductance. These are illustrative company assumptions, not general bill-of-materials statistics or a guaranteed saving.
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- Semiconductor, driver, isolated-power and protection-component costs.
- Magnetics, capacitors, filters, snubbers and current sensors.
- Heat sink, fan, cold plate, enclosure and acoustic-control costs.
- Printed-circuit-board layers, creepage spacing, assembly yield and inspection time.
- Firmware, control-development and validation effort caused by different switching behavior.
- Warranty, service, field-failure and energy-consumption costs over the intended life.
- Supply continuity, second-source availability and qualification cost at the target production volume.
TI’s 2020 article includes a normalized future device-cost model with a superjunction MOSFET baseline of 1.0, GaN at 1.3 and SiC at 2.4. The model excludes depreciation and is historical; it should not be read as current retail pricing. Device prices vary by rating, package, volume and market conditions.
Why mixed-technology architectures are often optimal
SiC and GaN are not mutually exclusive. TI’s overview says the technologies serve different voltage, power and application needs while overlapping in some equipment. Onsemi states that “Modern power systems often combine all three technologies, optimized by stage rather than replaced wholesale.” A product might therefore use SiC in a high-voltage AC/DC front end, GaN in an isolated high-frequency DC/DC stage and silicon in a low-cost auxiliary supply.
Choose independently for each stage, then verify that the interfaces work together. A fast GaN stage can impose a common-mode-current or EMI problem on a downstream motor cable. A SiC front end can reduce losses while its switching frequency remains low enough to avoid the gate-drive and measurement complexity of GaN. Shared cooling, control timing, isolation barriers and fault handling must be included in the architecture review.
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A practical selection workflow
- Write the electrical envelope. Record input range, DC-link voltage, output voltage, continuous and peak power, current, transient conditions and required blocking margin.
- Partition the power tree. Separate PFC, inverter, transformer-isolated DC/DC, point-of-load and auxiliary stages. Do not assign one semiconductor technology to the whole product by default.
- Choose candidate voltage classes. Use current manufacturer datasheets for the exact rating. Treat the 2020 TI descriptions and onsemi’s architecture ranges as orientation, not substitutes for a part specification.
- Select a topology and switching target. Determine whether hard switching, resonant switching, zero-voltage switching or zero-current switching is realistic at every load point.
- Build first-order loss models. Use datasheet RDS(on), charge, capacitance, switching-energy and reverse-conduction data at the actual temperature and voltage. Add gate-drive, magnetic, capacitor and snubber losses.
- Design the thermal path. Calculate junction temperature with worst-case ambient, interface resistance, airflow or coolant limits and component tolerances.
- Lay out and simulate the commutation loop. Estimate parasitic inductance and capacitance, then verify overshoot, ringing, dead time and common-mode current with appropriate measurement techniques.
- Check protection and qualification. Confirm short-circuit response, overvoltage clamping, isolation, humidity and temperature cycling, production test access and required reliability evidence.
- Compare total cost and supply risk. Price the complete stage at the intended volume and include passive reduction, cooling, PCB area, development time and second-source plans.
- Prototype at the real corners. Test minimum and maximum input, light and full load, hot and cold conditions, startup, shutdown, faults and the intended enclosure. Do not extrapolate a room-temperature bench result to the production system.
Common selection mistakes and how to correct them
“GaN is always cheaper”
Correct the comparison by calculating complete system cost. GaN may reduce magnetics, cooling and enclosure size, while the device, driver, layout and validation may cost more. The result depends on power level, volume and frequency.
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“SiC is always more efficient”
Efficiency depends on voltage, current, frequency, topology, temperature and commutation conditions. A GaN stage can win at high frequency and moderate voltage; a SiC stage can win at high voltage and high power. Compare measured or datasheet-based losses at the same operating point.
Using a voltage range as a guaranteed product limit
Vendor technology pages describe families and architectures, not a promise that every product reaches the upper boundary. Verify rated voltage, derating, surge capability, qualification and availability for the exact part.
Ignoring reverse conduction and dead time
Half-bridge loss can be dominated by the interval between switches. Model reverse-conduction voltage, body-diode or channel behavior, dead time and commutation current rather than comparing only RDS(on).
Assuming higher frequency automatically means higher density
Higher frequency can shrink magnetics but increase switching loss, EMI-filter size, gate-drive loss and thermal stress. Optimize frequency for the complete converter, not for the switch alone.
Copying a reference design without its conditions
A reference design’s power, cooling, PCB stack-up, switching frequency, load profile and test limits are part of its result. Recalculate for your bus voltage, ambient temperature, production tolerances and safety requirements.
Decision guide by application
| Application profile | First technology to investigate | Why | Important qualification questions |
|---|---|---|---|
| Traction inverter or high-power industrial drive | SiC | High bus voltage, current and thermal cycling are central constraints. | Short-circuit withstand, module reliability, cooling plate, switching frequency and motor insulation. |
| Solar inverter, storage converter, UPS or DC fast charger | SiC for the high-voltage power stage | Energy-infrastructure stages often prioritize voltage and power capability. | Grid code, isolation, fault ride-through, EMI, service life and parallel-device current sharing. |
| USB Type-C adapter or compact server supply | GaN | Power density and high-frequency magnetics can reduce size. | Thermal enclosure, EMI, no-load consumption, isolation, transient response and certification. |
| Isolated DC/DC intermediate bus | GaN or SiC depending on voltage and power | GaN can favor high frequency; SiC can favor higher voltage and power. | Transformer insulation, soft-switching range, duty-cycle limits and fault protection. |
| Point-of-load regulator | GaN at suitable voltage; silicon remains possible | Fast switching can reduce inductance and improve response. | Current ripple, controller compatibility, package thermal resistance and cost at volume. |
| Multi-stage converter | Mixed technologies | Each stage can be optimized for its own voltage, frequency and thermal job. | EMI interaction, shared cooling, control coordination and supply-chain complexity. |
What evidence is strong enough for a final choice?
Use vendor technology pages and application articles to identify plausible architectures, but use the exact device datasheet, evaluation-board documentation, qualification reports and your own test data to approve a design. The cited TI overview is from the fourth quarter of 2020 and is best treated as an attributed technical map. Onsemi’s GaN and energy-infrastructure pages were current pages consulted in October 2026; their application and product statements remain vendor claims rather than independent comparative testing. Onsemi’s SiC cost article, published July 26, 2023, provides an illustrative economic argument rather than a neutral market survey.
No single published figure settles the SiC-versus-GaN question. A credible decision record should show the operating points, loss calculations, thermal assumptions, measured waveforms, protection margins, costed bill of materials and supply-risk assessment for the actual product.
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Final recommendation
Begin with SiC for high-voltage, high-power front ends, traction and energy infrastructure; begin with GaN for compact, high-frequency stages where switching speed can materially reduce passive size and thermal burden. Then challenge that first choice with a stage-level comparison using real device ratings, topology, gate drive, layout, cooling, reliability and total cost. If the product has multiple stages, expect the best answer to combine technologies rather than declare one universal winner.
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