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A semiconductor fab is not built around one “chip-making machine.” It is a tightly integrated production line of deposition, patterning, removal, modification, cleaning, measurement, and packaging tools. The front-end sequence is repeated for every device layer: deposit material, coat photoresist, expose the pattern, bake and develop it, etch the underlying film, implant dopants where required, strip and clean the wafer, then measure the result. Wafers are eventually diced, tested, and packaged into finished components.
The right buying decision therefore starts with the device, wafer size, process node, layer stack, yield targets, and factory infrastructure—not with a vendor brochure. This guide maps each process step to the equipment a fab must specify, explains the performance metrics that matter, and shows how tools connect into an automated, contamination-controlled production system.
What equipment does a semiconductor fab need?
A complete fab typically needs equipment in ten connected categories:
- Wafer-cleaning and thermal-processing systems
- Thin-film deposition tools
- Photoresist coat, bake, and develop tracks
- EUV or DUV lithography scanners and reticle handling
- Dry-plasma and wet-etch systems
- Ion implantation and dopant-activation tools
- Photoresist-strip and wafer-cleaning equipment
- Chemical-mechanical planarization (CMP) and post-CMP cleaning
- Inspection and metrology systems
- Wafer sort, dicing, assembly, and package-test equipment
These categories are interdependent. A scanner can print a pattern accurately only if the deposited film is uniform and the wafer surface is flat. An etcher can transfer that pattern only if its plasma chemistry is selective and stable. Metrology must detect drift quickly enough for engineers to correct recipes before defects spread across a lot. A purchasing plan that omits any one of those feedback loops can produce technically impressive tools but poor yield.
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ASML’s process explainer says microchip manufacturing involves hundreds of steps and can take up to four months from design to mass production. ASML also describes a complete chip as requiring the layer-building sequence to be repeated as many as 100 times. The exact count depends on the device and process, but the implication is constant: a fab buys a repeatable ecosystem, not a single machine.
How the front-end process loop works
Most front-end-of-line (FEOL) and back-end-of-line (BEOL) layers follow a variation of this loop:
- Prepare the wafer: clean the surface and establish the required thermal or material condition.
- Deposit a film: add a dielectric, semiconductor, barrier, seed, or metal layer.
- Coat with photoresist: spin-coat resist and bake it to achieve a controlled film.
- Expose the pattern: project a reticle image with EUV or DUV lithography.
- Bake and develop: chemically amplify or stabilize the resist, then remove selected areas.
- Etch: transfer the resist image into the underlying film.
- Modify the wafer: implant dopants or perform another selective treatment where the layer requires it.
- Strip and clean: remove resist, particles, residues, and edge contamination.
- Planarize when needed: use CMP to flatten topography before the next critical layer.
- Measure and inspect: check dimensions, overlay, film properties, and defects; feed results back into process control.
The sequence is not strictly linear. Cleaning may occur several times within a layer, CMP can precede or follow different modules, and some layers skip implantation. The important buying principle is that every tool must meet the process window established by the neighboring tools.
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1. Wafer preparation and thermal treatment
Before patterning begins, wafers pass through cleaning benches and thermal systems. Cleaning removes particles, organic films, native oxides, and metallic contamination that could affect adhesion or electrical behavior. Oxidation, diffusion, furnace, and rapid-thermal systems then grow or modify films and set material properties.
Specify the wafer diameter and loading format first. The tool must maintain temperature uniformity across the wafer, repeat recipes accurately, and prevent cross-contamination between materials. Chemical-delivery cabinets, exhaust treatment, and point-of-use filtration are part of the purchase even when they appear outside the core equipment quotation.
- Key specifications: wafer size, temperature range and uniformity, ramp rate, atmosphere control, batch or single-wafer operation, contamination performance, and recipe repeatability.
- Factory interfaces: chemical supply, process gases, exhaust, chilled water, electrical power, automation, and wafer-handling standards.
- Common failure mode: a stable center-of-wafer result with poor edge behavior. Check wafer clamping, gas flow, heater zoning, edge exclusion, and calibration rather than changing the recipe blindly.
2. Thin-film deposition
Deposition tools add the films that become transistors, isolation layers, barriers, liners, interconnects, and other structures. The main equipment families are chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), epitaxy, and electrochemical deposition.
CVD uses reactive gases to form films; PVD transfers material from a target in a vacuum; ALD builds highly controlled films through repeated, self-limiting surface reactions; epitaxy grows a crystalline layer aligned with the substrate; electrochemical deposition fills or coats conductive features from a liquid bath. The process choice depends on the material, feature geometry, required conformality, and thermal budget.
| Deposition family | Typical buying focus | Questions to ask suppliers |
|---|---|---|
| CVD | Film composition, thickness uniformity, conformality, precursor compatibility, throughput | How stable is the chemistry across chamber age and lot transitions? What by-products require abatement? |
| PVD | Step coverage, target utilization, particle control, stress, deposition rate | Can the system maintain film properties across the wafer and over target life? |
| ALD | Atomic-scale thickness control, conformality, cycle time, precursor delivery | What is the minimum practical cycle time, and how is precursor saturation verified? |
| Epitaxy | Crystal quality, dopant control, uniformity, thermal budget | How are defects, loading effects, and wafer-to-wafer composition variation monitored? |
| Electrochemical deposition | Void-free fill, bath control, current distribution, chemical consumption | How are bath chemistry, replenishment, filtration, and endpoint conditions managed? |
Do not compare deposition tools on deposition rate alone. Film thickness and composition uniformity, defectivity, conformality in high-aspect-ratio features, precursor cost, chamber cleaning, and uptime determine the real cost of ownership.
3. Photoresist coating, baking, and developing
Track systems combine resist coating, bake plates, develop modules, and wafer handling. They create the photoresist film that lithography will expose and then convert the latent image into a physical mask.
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Coat uniformity affects critical dimensions (CDs), while bake temperature and time affect resist chemistry and pattern stability. Development must remove the intended regions without scumming, footing, or pattern collapse. The track should support the resist chemistry, wafer size, exposure platform, and factory automation standard used by the fab.
- Specify: resist and solvent compatibility, film-thickness range, coat uniformity, bake-plate uniformity, develop control, defectivity, wafer size, and integration with the scanner.
- Watch for: bubbles, streaks, edge-bead problems, particles from transfer arms, and queue-time sensitivity between coat, exposure, and develop.
- Integration requirement: the track, scanner, and metrology system must share lot identity, recipes, and wafer-history data so exposure corrections are based on the actual resist condition.
4. Lithography exposure
Lithography projects a circuit pattern from a reticle onto photoresist. A projection system shrinks and focuses the reticle image onto the wafer while a precision stage positions each field. EUV is used for the smallest and most critical layers; DUV serves less-critical layers with larger feature requirements and remains part of advanced production flows.
The scanner is only one part of the lithography module. Reticle inspection and storage, pellicle handling where applicable, wafer alignment, focus control, dose control, and overlay metrology all affect printed performance.
| Buying axis | Why it matters |
|---|---|
| Resolution | Determines the smallest feature the exposure process can print within the required process window. |
| Overlay | Controls alignment between the current layer and previously patterned layers. |
| Critical-dimension control | Limits line-width variation across fields, wafers, and lots. |
| Source power and throughput | Set exposure productivity and influence the number of wafers the fab can process per day. |
| Uptime and maintainability | Determine whether theoretical throughput is available in production. |
| Reticle and wafer handling | Protects masks and wafers from particles, scratches, and misalignment. |
Choose lithography by layer requirements, not by the most advanced label. A layer that does not need EUV resolution may be more economically printed with DUV, provided overlay, CD, and defect targets are met. The correct mix is a process-integration decision.
5. Etch
Etch removes selected material so the resist pattern becomes a three-dimensional structure in the film below. Dry plasma or reactive-ion etch (RIE) is used to define most circuit features. Wet etch uses liquid chemistries for cleaning and for selected material-removal steps where its selectivity and isotropy are advantageous.
Etch buyers should separate pattern fidelity from simple removal rate. A fast process that rounds corners, undercuts a line, or varies with chamber condition can reduce yield.
- Selectivity: the etch must remove the target film faster than the resist, mask, or underlying stop layer.
- Anisotropy: vertical sidewalls are often required for dense features and high-aspect-ratio structures.
- Profile control: taper, bowing, footing, notching, and microloading must remain inside the process window.
- Uniformity: center-to-edge and wafer-to-wafer behavior must be predictable.
- Chamber condition: wall coatings, seasoning, clean frequency, and by-products influence repeatability.
Require chamber-health data and a plan for endpoint detection. Endpoint signals, optical emission, interferometry, or timed recipes may be used depending on the film stack. The supplier should show how process drift is detected before it becomes a lot-level excursion.
6. Ion implantation and dopant activation
Ion implanters introduce controlled amounts of dopant at selected energies and doses. Subsequent furnace or rapid-thermal processing activates dopants and repairs implantation damage while limiting unwanted diffusion.
Specify dose and energy ranges for the device, beam-current capability, uniformity, wafer handling, and automation. Thermal tools must be evaluated as part of the same module because activation temperature and time determine the final electrical profile.
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- Beam uniformity and dose accuracy across the wafer
- Energy control and depth distribution
- Damage control and particle performance
- Thermal budget and ramp-rate repeatability
- Throughput at the actual recipe mix, not only at a single high-current condition
For advanced devices, an implanter that meets nominal dose but cannot control angle, edge behavior, or thermal interaction with neighboring layers may still fail the integration target.
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Strip and clean tools remove photoresist, etch residues, particles, metals, and edge contamination between process modules. Plasma strip, wet benches, single-wafer cleaning, batch cleaning, and bevel-clean systems may all be required.
Cleaning is a yield-control operation, not a cosmetic step. ASML notes that a tiny particle can ruin a chip and describes ISO class 1 cleanroom conditions with no more than 10 particles between 100 and 200 nanometers per cubic meter and none larger than 200 nanometers in the cleanroom description. The equipment, chemicals, filtration, wafer handling, and facility airflow must work together to maintain that environment.
| Cleaning consideration | Procurement question |
|---|---|
| Particle adders | Does the tool remove contamination without introducing particles from chambers, brushes, nozzles, or handlers? |
| Chemical selectivity | Will the chemistry remove residue without attacking the film, liner, or low-k material that must remain? |
| Water and chemical consumption | What are the usage rates at the intended wafer mix, and how are chemicals recycled or abated? |
| Wafer stress | Could mechanical brushes, megasonic energy, drying, or thermal shock damage fragile structures? |
| Edge and bevel control | Does the system prevent edge contamination from migrating into later modules? |
8. CMP planarization and post-CMP cleaning
CMP combines chemical slurry with mechanical polishing to flatten wafer topography. Planarization keeps later lithography within focus and overlay budgets and enables controlled formation of structures such as interconnect layers.
Specify removal rate, within-wafer and wafer-to-wafer uniformity, dishing, erosion, endpoint control, slurry consumption, pad life, and defectivity. Dishing can recess a wide feature; erosion can remove more material from dense patterns. Both can change resistance and degrade subsequent lithography.
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Post-CMP cleaning is part of the CMP purchase. Slurry particles and residues must be removed without scratching the wafer or attacking exposed films. Ask for data at the actual pattern density and film stack, not only on blanket wafers.
9. Inspection and metrology
Inspection and metrology tools measure whether the process is doing what the recipe intends. Optical inspection finds defects over large areas; e-beam inspection provides higher sensitivity for selected applications; CD-SEM measures critical dimensions; overlay tools measure layer-to-layer alignment; film-thickness and mass-metrology systems characterize deposited or removed material.
Metrology is part of the production loop. Measurements feed corrections back to scanners, deposition chambers, etchers, implant recipes, and cleaning processes. ASML describes this inspection-and-feedback relationship as part of chip production, while equipment suppliers also position metrology as a way to control process drift.
| Tool type | Primary measurement | Main trade-off |
|---|---|---|
| Optical inspection | Particles and pattern defects over broad wafer areas | High coverage and speed versus lower sensitivity for some small defects |
| E-beam inspection | Fine defects and selected process signatures | Higher sensitivity versus slower sampling |
| CD-SEM | Line width, space, profile, and local dimensions | Detailed measurements versus limited sampling throughput |
| Overlay metrology | Alignment between successive layers | Accuracy and model quality versus measurement time |
| Film-thickness metrology | Thickness and sometimes optical or material properties | Fast non-destructive sampling versus stack-dependent uncertainty |
When comparing metrology, include measurement uncertainty, sampling plan, recipe flexibility, data latency, and integration with the fab’s manufacturing-execution and process-control systems. A highly sensitive instrument that reports too slowly to trigger a useful correction may contribute less than a slightly less sensitive tool with rapid feedback.
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10. Wafer sort, dicing, and packaging
After wafer fabrication, probe systems electrically test individual dies. Dicing saws or lasers separate the wafer, and assembly tools attach dies to packages using wire bonding, flip-chip interconnects, molding, or other package technologies. Final testers verify electrical performance before shipment.
Equipment selection depends on package type, die size, interconnect technology, thermal requirements, test coverage, and expected yield. Dicing precision affects edge damage and die strength. Die-attach accuracy affects thermal paths and alignment. Package-test capacity must match wafer-sort output so finished dies do not accumulate in a bottleneck.
- Probe and sort: contact reliability, parallel test capability, test coverage, and data traceability.
- Dicing: kerf control, chipping, die strength, throughput, and compatibility with wafer thickness.
- Assembly: placement accuracy, bonding method, package materials, thermal performance, and rework policy.
- Final test: electrical coverage, temperature range, binning, throughput, and failure analysis connectivity.
Which companies make semiconductor manufacturing equipment?
The supplier landscape is specialized rather than interchangeable.
ASML
ASML is best known for lithography systems. Its documentation distinguishes EUV systems for the smallest and most critical layers from DUV systems for less-critical, larger-feature layers. Its production descriptions also emphasize metrology and inspection feedback around exposure.
Applied Materials
Applied Materials describes a portfolio spanning materials deposition, CMP, etch, pattern shaping, photomask, ion implantation, thermal processing, materials analysis, and patterning control. A fab may therefore evaluate it across several modules while still qualifying each tool against the specific process step.
Lam Research
Lam Research documents equipment for thin-film deposition, plasma etch, photoresist strip, wafer cleaning, and high-precision mass metrology. These modules often sit close together in the repeating pattern-transfer loop, so chamber stability and data integration deserve as much attention as headline specifications.
These suppliers are examples of major equipment categories, not substitutes for a process-qualified bill of equipment. A fab may use multiple suppliers because no single company necessarily provides the best tool for every material, node, package, or factory constraint.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to specify and buy fab equipment
Step 1: Define the process and wafer scope
- State wafer diameter, wafer thickness range, notch or flat orientation, and carrier format.
- Identify the device type, process node, layer count, and FEOL or BEOL modules included.
- List all materials, gases, liquids, masks, and temperature-sensitive structures the tool must handle.
- Set the expected production mix, lot size, operating hours, and qualification schedule.
Step 2: Set measurable performance targets
Translate the process window into acceptance criteria. Depending on the module, this may include resolution, overlay, CD variation, film thickness and composition, within-wafer uniformity, defectivity, etch profile, implant dose, removal rate, CMP dishing, uptime, and throughput. Define how each metric will be measured, on what wafer type, and over what period.
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Request a complete facilities matrix covering electrical power, process gases, chemical delivery, exhaust and abatement, chilled water, compressed air, vacuum, drainage, floor loading, heat output, vibration, and cleanroom interfaces. Include consumables such as targets, precursors, slurry, filters, pads, lamps, seals, and chamber kits. A tool that fits the process but exceeds site capacity is not deployable.
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Require factory-automation interfaces, recipe management, wafer and lot tracking, alarm handling, preventive-maintenance records, and time-stamped data export. Confirm that the tool can exchange results with metrology and process-control systems. Traceability should cover recipe revisions, chamber state, operator actions, maintenance events, and material lots.
Step 5: Compare total cost of ownership
Installed price is only one part of the decision. Model consumables, utilities, preventive maintenance, chamber cleans, spare parts, service contracts, qualification wafers, downtime, floor space, abatement, and decommissioning. Compare cost per qualified wafer at the planned recipe mix rather than cost per wafer under an ideal single recipe.
Step 6: Qualify before volume purchase
- Run supplier demonstrations using representative films, patterns, and wafer handling.
- Measure the agreed acceptance criteria with calibrated fab metrology.
- Test repeatability across wafers, lots, chambers, shifts, and maintenance cycles.
- Check integration with upstream and downstream tools, automation, and data systems.
- Release the tool for production only after yield, reliability, process-window, and recovery targets are met.
Common buying mistakes and how to avoid them
Buying for a headline specification
A scanner’s nominal resolution, an etcher’s maximum rate, or a deposition tool’s best uniformity does not describe production performance. Ask for capability at the actual materials, pattern densities, wafer size, and maintenance interval.
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Particle performance can change after a clean, target replacement, seasoning cycle, or preventive-maintenance event. Require chamber-state tracking, particle adders, recovery procedures, and post-maintenance qualification criteria.
Separating process tools from metrology
Without timely measurements, process drift can continue through multiple lots. Define sampling frequency, measurement uncertainty, data latency, and automatic feedback actions during the initial equipment specification.
Underestimating infrastructure
Gases, chemicals, exhaust, chilled water, abatement, vibration isolation, and cleanroom airflow are production systems. Obtain facility drawings and utility consumption at the intended throughput before signing the final layout.
Optimizing one module at the expense of the line
A faster deposition tool does not increase output if lithography, cleaning, inspection, or packaging is the bottleneck. Use line-level capacity modeling and include queue time, changeovers, maintenance, and lot movement.
A practical equipment decision framework
Use this sequence when comparing qualified tools:
- Process fit: Can the tool run every required material, geometry, and thermal condition?
- Capability: Does it meet uniformity, defectivity, dimensional, and reliability limits with margin?
- Productivity: What is the demonstrated throughput after loading, alignment, recipe changes, cleaning, and maintenance?
- Integration: Can it exchange recipes, identifiers, alarms, and measurements with the rest of the fab?
- Ownership: What are utilities, consumables, spare parts, service response, training, and expected downtime?
- Scale and support: Can the supplier provide parts, upgrades, process support, and service coverage for the intended geography and production life?
Score each category separately. A tool should not win because it has the lowest purchase price if it creates a larger metrology burden, uses more chemicals, or cannot recover quickly after maintenance.
What a complete fab buyer should remember
- The repeating production loop is deposition, resist coating, lithography, bake/develop, etch, optional implantation, strip and clean, planarization where required, and metrology.
- EUV and DUV lithography serve different layer requirements; the most advanced exposure system is not automatically the right choice for every layer.
- Dry plasma etch transfers patterns, while wet processes are used mainly for cleaning and selected removal operations.
- Metrology and inspection provide feedback that stabilizes the process; they are production equipment, not optional laboratory accessories.
- Contamination control extends from ISO-class cleanroom airflow to chamber surfaces, wafer handlers, chemicals, and maintenance procedures.
- Qualification must measure the integrated line, because yield depends on interactions among tools rather than isolated specifications.
A semiconductor fab succeeds when every machine delivers a predictable wafer to the next machine. Buy against that complete process chain—with defined materials, data interfaces, contamination controls, utilities, and acceptance tests—and the equipment list becomes a manageable production architecture rather than a collection of disconnected capital purchases.
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