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Short answer: Samsung Foundry and TSMC both report production-ready 2nm-class processes, but public disclosures do not prove that their nodes have equal maturity or yield. Samsung says SF2 entered mass production in 2025, while TSMC says N2 entered volume production in the fourth quarter of 2025. TSMC describes N2 yield as good and expects a fast 2026 ramp; Samsung says it is working to stabilize advanced-node mass-production yields. Neither supplier publishes a comparable, independently audited yield percentage for equivalent designs.
For an actual chip program, the better choice is not determined by the words SF2 or N2. Compare the exact process revision, design rules, PDK and IP readiness, design-specific qualification data, packaging route, geographic and capacity requirements, and the support team assigned to your account. The comparison below separates what each company publicly reports from what a buyer still has to verify.
What this comparison can—and cannot—tell you
This is a comparison of public company disclosures, not a customer audit, laboratory test, or production qualification. Samsung and TSMC describe their own process status, services, and business scale, but those descriptions do not measure how a particular customer project will perform. A leading-edge process can be available in general while a specific design still faces incomplete IP, immature design rules, limited capacity, packaging constraints, or yield learning.
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Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →The most important unanswered procurement question is whether either supplier will provide comparable, independently audited, customer-design-specific yield and support-response data. Publicly available company materials do not establish that evidence. Treat the tables in this guide as a framework for due diligence, not as a ranking of manufacturing quality.
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Samsung Foundry vs TSMC process nodes and production status
| Supplier and process | Publicly reported status | What the statement does not establish |
|---|---|---|
| Samsung SF2 | Samsung’s logic-node page says SF2 started mass production in 2025. Samsung describes SF2 as building on its MBCFET gate-all-around process. | The statement is Samsung’s reported status. It does not independently verify shipment volume, customer adoption, wafer capacity, qualification results, or yield. |
| TSMC N2 | TSMC’s 2nm Technology page says N2 began volume production in the fourth quarter of 2025 as planned. TSMC’s 2025 annual report describes progress in yield and performance, calls the yield good, and expects a fast ramp in 2026. | TSMC does not give a percentage in the cited annual-report passage. The wording does not make N2 directly comparable with SF2 or prove equivalent maturity. |
| TSMC 3nm extensions | TSMC’s technology material lists N3X volume production in 2025 and N3C in 2026. | Those dates describe TSMC’s portfolio schedule. They do not indicate that a particular product can use every variant immediately or that the variants have identical rules, IP, cost, or capacity. |
Samsung SF2: what the public record says
Samsung positions SF2 as part of a portfolio that runs from legacy technologies through 2nm. Its process page identifies 2025 as the start of SF2 mass production and links the node to the company’s MBCFET gate-all-around approach. “Mass production” is a meaningful status signal, but it is not a substitute for a customer-specific qualification report. A buyer still needs the exact SF2 revision, available design kits, approved IP, wafer-start allocation, package path, and acceptance criteria for the product.
Samsung’s 2025 business-report discussion also says its advanced-node work is focused on stabilizing mass-production yields and attracting customers. That language indicates ongoing yield learning and commercial development; it should not be interpreted as a numerical yield disclosure. Read it alongside the specific program data Samsung offers under nondisclosure.
TSMC N2: what the public record says
TSMC says N2 entered volume production in the fourth quarter of 2025 as planned. In its 2025 annual report, the company says N2 development progressed in yield and performance, characterizes the yield as good, and forecasts a fast ramp in 2026. “Good” is qualitative: the cited passage supplies no die-yield percentage, defect-density value, product list, or independent verification.
TSMC also continues to extend its 3nm family. The N3X and N3C dates matter when a design needs a mature alternative to a newly ramping 2nm node, but the best option depends on the product’s performance-per-watt target, library support, mask cost, package, and available capacity. A nominally older node may be the lower-risk choice for a high-volume launch.
Why “2nm” is not an apples-to-apples specification
Process names are vendor-defined family labels. Samsung SF2 and TSMC N2 should not be assumed to have the same physical dimensions, transistor density, performance, power characteristics, design rules, mask complexity, wafer price, or maturity simply because both use “2nm” in the name.
For a fair comparison, request the actual process variant and revision rather than a node label. The relevant data set normally includes standard-cell libraries, SRAM options, design-rule manuals, PDK release and qualification status, available interface and memory IP, reliability rules, expected operating corners, and package-specific electrical limits. Compare the numbers for the same design objective—such as maximum frequency at a defined voltage and power envelope—not headline claims made under different conditions.
It is also possible for two variants in one vendor’s family to have materially different economics. A high-performance option may require more restrictive rules or additional masks, while a lower-power or automotive-qualified option may trade peak speed for reliability and temperature range. Ask each supplier to identify exactly which variant their quotation and schedule cover.
Yield: what is known, what is missing, and why it matters
No comparable public percentage exists
Publicly available Samsung and TSMC materials do not provide a supported, independently audited, side-by-side yield percentage for comparable Samsung and TSMC nodes. Samsung’s 2025 report discusses stabilizing advanced-node mass-production yields. TSMC’s 2025 annual report calls N2 yield good but gives no percentage in the cited passage. These statements use different levels of specificity and cannot be converted into a ranking.
| Evidence | How to interpret it |
|---|---|
| Samsung 2025 business report: advanced-node work focuses on stabilizing mass-production yields and attracting customers (report PDF) | A company description of an ongoing ramp and customer-development priority; no percentage or design-specific result is stated. |
| TSMC 2025 annual report: N2 yield is described as good, with a fast 2026 ramp expected (annual report PDF) | A qualitative company statement; no percentage, product mix, test limits, or independent audit is stated. |
| Samsung 2021 statement about 3nm logic yield (Samsung Global Newsroom) | Historical context only: Samsung said in 2021 that 3nm yield was approaching a level similar to its 4nm process. It is not a current SF2 figure and is not a comparison with TSMC. |
What a yield number should include
“Yield” can refer to different measurements. Wafer sort yield, known-good-die yield, final-test yield, package yield, and the percentage of dies meeting a particular speed or power bin are not interchangeable. A reported figure is meaningful only with its process revision, product design, die area, defect criteria, test stage, wafer date, and ramp point.
Large dies generally expose more opportunities for defects than small dies. Memory arrays, analog blocks, high-speed interfaces, and dense compute logic can respond differently to the same process. A process may show strong average wafer yield while a specific product has a lower yield because it uses a difficult IP block or a demanding frequency bin. Product mix and binning also change the economics: a die that passes at a lower speed may still be saleable in another product tier.
Questions to ask for design-relevant evidence
- What is the current yield for this exact process revision and a die of similar area and complexity?
- Is the figure wafer sort, final electrical test, package yield, or the percentage meeting our target bin?
- Which wafer lots and production dates are represented, and how has the number changed during the ramp?
- What defect-density, parametric-yield, reliability, and infant-mortality data will be shared under confidentiality?
- Which IP blocks, memory compilers, libraries, and package technologies were included in the qualification vehicle?
- What yield assumption is used in the commercial quotation, capacity reservation, and supply agreement?
Ask both suppliers the same questions and record the answer date, process revision, test definition, and confidentiality restrictions. Without that normalization, a percentage from one supplier can look better simply because it measures an easier test stage.
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Both companies describe broad support organizations. Those descriptions establish the services they say they offer; they do not prove that every account receives the same response time, engineering depth, or escalation quality.
| Support area | Samsung Foundry’s public description | TSMC’s public description |
|---|---|---|
| Design platform | Samsung describes a total design platform covering libraries, PDKs, design methodology, IP, design support, packaging, and cloud services in its About Samsung Foundry material. | TSMC describes integrated foundry services spanning advanced and specialty technologies, mask services, advanced packaging, manufacturing quality, and design-ecosystem support in its Dedicated IC Foundry information and annual report. |
| Customer and application assistance | Samsung says it has dedicated customer teams and application-specific services. The public page does not specify response-time targets or staffing for a particular account. | TSMC says it provides customer support, account management, and engineering services through offices in North America, Europe, Japan, China, and South Korea. The public description does not specify the service level for a particular program. |
| Packaging | Packaging is included in Samsung’s described design platform; the exact package technologies and availability must be confirmed for the selected process and site. | Advanced packaging is included in TSMC’s integrated foundry-service description; the exact package, interposer, chiplet, and allocation details must be confirmed for the program. |
Samsung’s support model
Samsung’s stated platform is broader than wafer fabrication alone. Libraries, PDKs, methodology guidance, IP, packaging, cloud access, and application-specific services can reduce the number of separate suppliers a design team must coordinate. The practical question is whether the required versions are released and qualified for your design window. Request a dated PDK roadmap, a list of production-qualified IP, an issue-tracking and escalation process, and named owners for design, manufacturing, and packaging.
Samsung’s manufacturing-site information describes regional fab and engineering arrangements, including Austin and Taylor in Texas and collaboration with Korea’s manufacturing network. Use the manufacturing-sites page to identify the stated locations, then ask which site will actually process your wafers, where engineering decisions are made, and whether a transfer between sites is qualified for your product.
TSMC’s support model
TSMC presents an integrated service model that combines process technologies, mask services, advanced packaging, manufacturing quality, and ecosystem support. Its annual report and foundry pages describe account management and engineering assistance backed by regional offices in North America, Europe, Japan, China, and South Korea. For a real project, ask whether your account receives a dedicated process-integration engineer, design-technology liaison, package specialist, and yield task force, and define the escalation path in writing.
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TSMC reports that it manufactured 12,682 different products using 305 distinct technologies for 534 different customers during 2025, according to its Dedicated IC Foundry information. These are company-reported scale figures, not market-share statistics and not matching Samsung figures. Large scale can indicate a broad ecosystem, but it can also mean your program must compete for attention and capacity; only the proposed account structure and service-level commitments answer that question.
Best Value
Packaging, geography, and capacity can outweigh a node-label advantage
A chip is not finished when the wafer leaves the fab. Package substrate, interposer or bridge technology, thermal limits, memory integration, high-speed signal integrity, and final-test capacity can determine whether the product meets its launch date. Ask each supplier to quote the complete path: wafer fabrication, bumping, assembly, package test, known-good-die handling, and any chiplet or high-bandwidth-memory integration required.
Manufacturing geography matters for continuity, export controls, logistics, customer qualification, and regulatory requirements. Map the proposed wafer and package sites, backup capacity, transit time, and change-notification process. Samsung’s public site information names facilities in Texas and Korea; TSMC’s public support description names regional offices, but the cited materials do not provide a like-for-like fab-capacity table for this comparison. Do not infer geographic equivalence from office locations.
Capacity should be evaluated in wafers per month for your exact variant and time window, not from a vendor’s total company scale. Obtain a committed wafer-start schedule, lead-time assumptions, allocation rules during shortages, and the conditions under which the supplier can move production to another qualified site. A theoretically faster node is not useful if it cannot support the required volume or package ramp.
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- Freeze the product requirements. Document performance, power, area, die size, operating temperature, reliability grade, package, annual volume, launch date, and acceptable cost. Without a fixed target, process comparisons become marketing comparisons.
- Name the exact process variant. Replace broad terms such as 2nm or 3nm with the vendor’s full variant, revision, voltage options, SRAM choice, and qualification status.
- Audit design enablement. Compare PDK release dates, design-rule stability, standard-cell and memory-library availability, interface IP, analog and RF options, EDA certification, cloud access, and known limitations.
- Run a design-specific qualification vehicle. Use a representative block or shuttle to measure parametric yield, defect sensitivity, frequency and power distributions, SRAM behavior, reliability, and package interaction. Do not substitute a vendor-wide adjective such as good for this evidence.
- Normalize yield data. Require the same test stage, die-area range, bin definition, wafer age, and reporting period from both suppliers. Record whether numbers are measured, forecast, or contractual.
- Validate packaging and supply. Confirm package technology, assembly location, substrate and interposer availability, thermal solution, test capacity, wafer allocation, lead time, and qualified backup routes.
- Score support operationally. Put named engineering contacts, response-time targets, escalation levels, bug-tracking access, PDK issue closure, and design-review milestones into the statement of work.
- Model total program risk. Include mask and NRE costs, expected scrap and rework, qualification time, schedule risk, logistics, currency and regional exposure, and the cost of changing suppliers after tape-out.
Supplier questions that expose the real differences
Process and PDK
- Which exact process revision is available for our tape-out date, and what changes are planned before risk production?
- Which PDK release is production-qualified, and what are the open known issues?
- Which libraries, SRAM compilers, analog blocks, SerDes, PCIe, memory interfaces, and security IP are available now rather than on a roadmap?
- What design-rule changes are expected after our first tape-out, and how are mask respins handled?
Yield and reliability
- What customer-design-specific qualification data can be shared under NDA?
- How are wafer sort, final test, package yield, and performance-bin yield reported separately?
- What reliability testing, operating corners, electromigration rules, and temperature qualifications apply to this variant?
- What corrective-action process is triggered when a lot misses the agreed yield or defect target?
Support and schedule
- Who owns process integration, PDK issues, IP issues, packaging, and yield during bring-up?
- What are the response and escalation times for blocking issues in design, mask data, wafer sort, and final test?
- Which engineering and manufacturing sites will support the account, and can the team work in the customer’s time zone?
- What capacity is reserved, what is the minimum commitment, and how are shortages allocated?
Common mistakes in a Samsung-versus-TSMC decision
- Treating node names as measurements. A 2nm label does not establish equal density, power, speed, cost, or maturity.
- Turning a qualitative yield claim into a percentage. “Good” and “stabilizing” describe different levels of information and cannot be ranked mathematically.
- Using old statements as current data. Samsung’s 2021 3nm comment is historical context, not evidence about 2026 SF2 yield.
- Comparing corporate scale with customer fit. TSMC’s 2025 product, technology, and customer counts show reported scale, not guaranteed capacity or support for your design.
- Ignoring the package. A wafer process can meet transistor targets while package, thermal, substrate, or test constraints derail the product.
- Accepting a service brochure as a service-level agreement. Require named contacts, dates, deliverables, and escalation commitments instead of relying on general descriptions.
- Failing to date every answer. Node status, PDK readiness, capacity, and yield change during a ramp. Record the process revision, wafer period, and scope of every supplier response.
How to read the public evidence responsibly
Company pages are useful for identifying claimed capabilities, production milestones, locations, and service categories. They are not independent audits. Samsung’s process and business pages establish what Samsung reports about SF2 and its design platform; TSMC’s process page, annual report, and foundry page establish what TSMC reports about N2, its ecosystem, and its 2025 scale. None of those pages supplies a normalized, customer-design-specific yield comparison.
The responsible conclusion is therefore conditional: both suppliers are credible candidates for advanced-node programs, but the public record cannot rank them on yield or customer support. The decision must be made from the exact process variant, qualification data, capacity and packaging plan, and the support commitments offered to the specific project.
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