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A model that works in a research demonstration may still be too slow, power-hungry or memory-intensive for a phone or wearable. On-device AI’s practical limits emerge when the model meets the whole device: memory, compute hardware, software, chip layout, packaging, power and heat. Physical design is a crucial part of that boundary, but it does not set it alone.
What limits on-device AI?
A model’s mathematical ability is only one part of whether it can run locally. The device must store the model’s weights, move data to the compute units, perform the operations and dissipate the resulting heat—all within limits on memory, power, latency, size and cost. A model may be accurate yet unsuitable for a particular device if meeting its response-time target drains the battery or forces sustained power beyond what the device can cool.
These constraints are especially visible at the edge, where compute, memory capacity and power budgets are generally tighter than in server environments. The 2021 survey Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design, by Cong Hao and co-authors, distinguishes among edge inference, edge training, caching and offloading. Those workloads should not be treated as interchangeable: running a trained model to answer a request is different from training or continually updating it on the device.
That distinction matters because a model’s demands depend on what it is doing, not just its parameter count. Inference is often the more common edge-AI workload, while training can impose different demands. A local inference benchmark therefore does not establish that the same device can train the model locally, and a result for continual learning is not a direct proxy for phone inference.
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Why model size is only part of the memory problem
Weights need somewhere to live, but inference also moves data and creates intermediate activations. If the working data does not fit in fast on-chip memory, the system may need to fetch it from memory outside the compute chip. Those transfers consume energy and time. The result is a memory wall: adding or optimizing compute does not necessarily make a workload faster if the data cannot reach it efficiently.
The 2021 Nature Electronics study of the Illusion system illustrates one way researchers have explored this problem. Its eight-chip system, which used networked computing chips with local memory and wakeup and shutdown mechanisms, came within 3.5% in energy and 2.5% in execution time of the study’s idealized single-chip reference with no off-chip memory. Those margins describe that paper’s DNN-inference setup and comparison—not a general guarantee for multi-chip systems, nor a result for consumer phones.
For deployment, the useful question is not simply “How large is the model?” It is whether the model’s weights and working data fit the target memory hierarchy, how often they must move, and what those transfers cost under the intended workload.
What physical design does—and what it cannot decide by itself
In VLSI, physical design transforms a netlist—a description of circuit connections and components—into a physical layout for fabrication. The work includes chip planning, placement, clock-tree synthesis, routing, physical verification and signoff. The layout must fit fabrication constraints while meeting goals for performance, power, yield and reliability.
Those choices affect how far signals travel, how components connect and how the implemented chip behaves. But physical design is one layer of a larger system. The model and its numerical precision affect the operations and data movement required. The architecture determines how those operations are organized. Memory technology and organization affect capacity and bandwidth; the compiler and runtime affect how work maps onto hardware; and the package shapes how chips connect and exchange power and data. A place-and-route team cannot independently erase a mismatch created elsewhere in the stack.
The practical ceiling is therefore a co-design problem, rather than a contest in which either algorithms or physical implementation always wins. Hao and co-authors’ 2021 survey describes edge-AI methods that include specialization at individual layers as well as cross-layer co-design, including software/hardware, software/compiler and compiler/hardware coordination.
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How packaging and thermal limits enter the design
A chip’s usable performance depends on more than the silicon die. Packaging and heterogeneous integration—the combination of different components or technologies in one system—are part of the design space because interconnects, power delivery and thermal management affect how components can work together. A larger or more capable package is not automatically better for every device: the gains must justify its power, heat, reliability, manufacturing and form-factor trade-offs.
A 2026 perspective in Nature Reviews Electrical Engineering considers heterogeneous integration across AI, high-performance computing, smartphones and communications. It identifies interconnects, power electronics, photonics, thermal management, reliability, modelling and co-design as relevant topics, and calls for coordination across design, manufacturing and reliability. This is a perspective on the field, not a quantified demonstration that a particular package improves phone performance.
Heat is a system constraint because a device has to sustain its workload, not merely produce a brief peak result. A benchmark that reports a fast run without specifying its power or thermal conditions may not show how the device behaves during longer use. Small devices have limited physical room for cooling, so implementation choices and the expected workload both matter.
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Why accelerator results need their workload and baseline
Research prototypes show what a particular combination of model, architecture and implementation can achieve. Their figures are useful only when read with the conditions attached. Two results are not directly comparable if they differ in model or task, batch size, precision, accuracy, memory configuration, latency measure, power envelope or baseline.
Thermal-aware chiplet design for edge-LLM continual learning
The 2025 Design Automation Conference paper on 3D-CIMlet presents a thermal-aware co-design framework for 2.5D and 3D edge-LLM engines built from heterogeneous compute-in-memory chiplets. For its continual-learning case study, the authors report maximum energy-efficiency gains of up to 9.3× and 12×, and energy-delay-product reductions of up to 90.2% and 92.5%, against 2D baselines for the studied designs. These are study-specific maxima, not measured gains for retail phones or a forecast for other workloads.
A latency-focused edge-LLM accelerator
The HALO accelerator paper reports a 12 nm implementation targeting 1 GHz, maximum power consumption of 15.58 W, and a 7.17× geometric-mean energy-efficiency improvement at batch size 1 versus the NVIDIA Jetson AGX Orin edge GPU. These figures belong to the paper’s implementation and comparison setup. They describe a specialized accelerator result, not a phone’s power budget or a general advantage for all edge inference.
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Read such claims by checking whether they use measured silicon, a prototype, simulation or an analytical projection; what model and task they run; and how latency, energy and accuracy are measured. The baseline matters too: a large gain over one design does not establish the same gain over another device or implementation.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why can’t AI models simply run locally on a phone?
Some can, depending on the model, task and phone. “Run locally” is not a single performance target: an application may prioritize a quick response, a long battery life, privacy, offline availability or sustained throughput, and those priorities can conflict. A model that fits in available memory may still miss its latency or power target; one that meets a short-run target may not sustain it under the device’s thermal limits.
The answer is not necessarily to shrink the model alone. Model specialization can reduce the work, while hardware, compiler and memory choices can help execute the remaining work more efficiently. The right combination depends on the target device and workload; the cited studies do not establish one configuration that is best for every phone.
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What a useful on-device AI benchmark should disclose
Before comparing claims about speed or efficiency, look for enough context to tell whether the systems did comparable work under comparable conditions. At a minimum, a meaningful report should identify:
- Workload and model: the task, model and, where relevant, whether the result is inference or training.
- Quality and numerical format: task accuracy and the precision used for computation.
- Batch regime and latency measure: batch size and whether the result concerns response latency, time to first token, throughput or another measure.
- Memory setup: capacity, bandwidth and relevant memory configuration.
- Power and thermal conditions: the stated power envelope and whether the measurement represents a brief run or sustained operation.
- Implementation and baseline: the hardware and package context, and the specific system used as the comparison.
- Evidence type: whether the result comes from measured silicon, a prototype, simulation or analytical projection.
Without these details, a headline multiplier may describe a different problem from the one a reader wants to solve.
The practical lesson: evaluate the model and device together
Research on models and algorithms remains central: it can change accuracy, computation, numerical precision and data movement. But those improvements become useful on a phone, wearable or other edge device only when the implementation can deliver them within its memory, latency, power and thermal limits. The most informative results therefore connect the model to the compiler, architecture, memory system, physical implementation and package—and state the workload and conditions under which they were measured.
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