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Short answer: NVIDIA Vera Rubin NVL72 and AMD Helios are both 72-accelerator, rack-scale systems for large-model training and inference, but they make different architectural bets. NVIDIA specifies a tightly integrated Vera CPU, Rubin GPU, sixth-generation NVLink, ConnectX-9, BlueField-4 and CUDA platform. AMD combines 72 Instinct MI455X GPUs with sixth-generation EPYC “Venice” CPUs, UALink/UALoE, Pensando networking and ROCm, using open rack and fabric standards.
AMD lists more aggregate HBM4 capacity—31 TB versus NVIDIA’s 20.7 TB—while NVIDIA emphasizes a co-designed rack with dedicated NVLink switch trays, liquid cooling and integrated power delivery. Those figures are vendor specifications, not a neutral benchmark. A defensible choice requires matched workload tests, software validation and facility engineering.
What these systems are—and what they are not
Neither product is a consumer graphics card or a conventional server that can be configured from independent parts. Each is an integrated rack-scale computer in which accelerators, host CPUs, high-speed fabrics, networking, power conversion, cooling and management are designed as one system.
The target workloads are distributed training, fine-tuning and inference for large language, multimodal and other high-parameter models. Keeping model weights, optimizer state, activations and key-value caches close to many accelerators is the reason the systems use rack-level memory and scale-up fabrics rather than relying only on ordinary PCIe links.
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The public specifications do not constitute a matched test. Peak FLOPS, aggregate memory bandwidth and network link totals are measured or calculated at different levels of each design. They do not by themselves establish which rack will deliver higher tokens per second, lower latency, better utilization or lower total cost for a particular model.
At-a-glance architecture comparison
| Dimension | NVIDIA Vera Rubin NVL72 | AMD Helios | How to interpret it |
|---|---|---|---|
| Accelerators | 72 Rubin GPUs | 72 Instinct MI455X GPUs | Both are 72-accelerator rack designs. |
| Host CPUs | 36 Vera CPUs | 18 sixth-generation EPYC “Venice” CPUs in AMD’s July 2026 launch configuration | CPU count is a system configuration, not a direct measure of host throughput or GPU feeding capacity. |
| Rack HBM4 | 20.7 TB | 31 TB | AMD lists the larger aggregate capacity; capacity is not the same as bandwidth or application performance. |
| GPU-memory bandwidth | 1,400 TB/s aggregate rack figure | 23.3 TB/s per GPU; about 1.68 PB/s when summed across 72 GPUs | The figures use different presentation methods. AMD’s rack sum is arithmetic from its per-GPU specification. |
| Scale-up fabric | Sixth-generation NVLink with nine switch trays; 216 TB/s on NVIDIA’s current product page | UALink/UALoE; 260 TB/s listed for Helios | Bandwidth scope and counting methodology must be verified before making a direct comparison. |
| Scale-out and management networking | ConnectX-9 for InfiniBand clustering; BlueField-4 for Ethernet storage and management | Pensando networking for front-end, scale-up and scale-out functions; Vulcano AI NICs are part of the rack design | Actual topology depends on the deployed cluster and storage design. |
| Software positioning | CUDA and the broader NVIDIA platform stack | ROCm open software stack | Framework, kernel and operations compatibility must be checked against the intended models. |
| Rack approach | Third-generation MGX design, modular cable-free trays and liquid cooling | OCP Open Rack Wide design with modular serviceability and integrated power, cooling and networking connections | “Open” and “integrated” describe design priorities, not guaranteed deployment simplicity. |
| Published status | NVIDIA says Vera Rubin is ramping into full production and shipping through manufacturing partners | AMD announced Helios in production in July 2026, with customer deployments and OEM availability | These are vendor statements made at different times, not an independently verified installed-base comparison. |
NVIDIA Vera Rubin NVL72 architecture
Compute trays and accelerator layout
NVIDIA’s current Vera Rubin product specification lists 72 Rubin GPUs and 36 Vera CPUs. The DGX Vera Rubin NVL72 hardware guide describes 18 one-rack-unit compute trays. Each tray contains two Vera CPUs and four Rubin GPUs, producing the published 36-CPU and 72-GPU totals.
The rack also includes nine NVLink 6 switch trays, two management top-of-rack switches and dedicated power shelves. The modular tray design is intended to reduce the amount of point-to-point cabling that technicians must handle during service.
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NVIDIA lists 20.7 TB of HBM4 across the rack and 1,400 TB/s of aggregate GPU-memory bandwidth. Its current product page also gives peak system figures of 3,600 PFLOPS for NVFP4 inference, 2,520 PFLOPS for NVFP4 training and 1,260 PFLOPS for FP8/FP6 training.
Those are NVIDIA-published peak specifications. They describe arithmetic capability under stated precisions, not sustained application throughput. Real results depend on model architecture, sequence length, sparsity, batch size, communication patterns, software versions and how much time the GPUs spend waiting on data.
NVLink bandwidth discrepancy
NVIDIA’s current product page specifies 216 TB/s of rack NVLink bandwidth. A separate NVIDIA newsroom announcement describes 260 TB/s for the NVL72 rack and states 3.6 TB/s per GPU. Because the manufacturer’s sources differ, a comparison should report the discrepancy rather than silently choosing the larger number. Procurement documents should identify which published specification and revision they use.
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Networking and platform integration
The DGX guide identifies ConnectX-9 adapters for InfiniBand clustering and BlueField-4 data-processing units for Ethernet storage and management. NVIDIA presents Vera Rubin as a platform-level co-design spanning CPUs, GPUs, networking, security, software, power and cooling. That approach can simplify validation when an organization already operates the NVIDIA software and networking stack, but it also makes the rack more dependent on that integrated ecosystem.
AMD Helios architecture
MI455X and EPYC composition
AMD’s Helios product page describes 72 Instinct MI455X GPUs. AMD’s July 2026 launch announcement specifies 18 sixth-generation EPYC “Venice” CPUs across the rack. The CPU-to-GPU ratio therefore differs from NVIDIA’s published configuration: one AMD CPU for every four GPUs versus one NVIDIA Vera CPU for every two GPUs. That ratio alone does not predict performance; memory topology, CPU capabilities, software scheduling and the amount of host-side work are equally important.
HBM4 capacity and component bandwidth
AMD lists 31 TB of rack HBM4, which is greater aggregate capacity than NVIDIA’s 20.7 TB. AMD’s CDNA architecture information specifies 432 GB of HBM4 and up to 23.3 TB/s of memory bandwidth per MI455X GPU. Multiplying the per-GPU bandwidth by 72 gives roughly 1.68 PB/s, while the Helios product page presents the per-GPU value rather than a single rack aggregate.
AMD also describes 3.6 TB/s of bidirectional GPU scale-up bandwidth for Helios and UALoE links within the rack. Component-level link rates and rack-level totals are not interchangeable; buyers should request the topology diagram and the exact bandwidth definition used in a quotation.
Open rack and networking strategy
Helios is positioned around UALink and UALoE, the OCP Open Rack Wide mechanical design and Ultra Ethernet Consortium standards. AMD describes Pensando networking for front-end, scale-up and scale-out paths and identifies Vulcano AI NICs in the rack design. This standards-oriented approach is intended to give system builders more choice in rack and network integration, while still requiring validation of firmware, collective-communication libraries, cabling and service procedures.
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Scale-up, scale-out and software: the practical differences
Scale-up inside one rack
Scale-up links connect the accelerators that participate in the same model-parallel or tensor-parallel job. NVIDIA uses NVLink 6 switch trays as the defining internal fabric. AMD uses UALink/UALoE. The advertised totals are not directly comparable unless both vendors state whether they count one direction or both directions, physical or effective bandwidth, and all links or only links available to GPU collectives.
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For a real workload, measure collective operations such as all-reduce, all-gather and reduce-scatter at the message sizes used by the model. A high theoretical link rate can be outweighed by software scheduling, topology oversubscription or synchronization overhead.
Scale-out between racks
NVIDIA’s documented design separates InfiniBand clustering from Ethernet storage and management functions through ConnectX-9 and BlueField-4. AMD describes Pensando-based networking that spans front-end, scale-up and scale-out roles. In either case, the rack is only one building block: the number of uplinks, switch radix, oversubscription policy, storage bandwidth and job scheduler determine multi-rack behavior.
CUDA and ROCm migration work
NVIDIA’s platform is built around CUDA and associated libraries and tools. AMD names ROCm as its open software stack. The relevant question is not which label sounds broader; it is whether the exact framework versions, custom kernels, quantization libraries, compiler options, monitoring tools and container images required by your models are supported.
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- Inventory CUDA-specific extensions, vendor kernels and inference engines before considering a move to ROCm.
- Confirm that ROCm versions support the framework release, GPU architecture and precision modes used in production.
- Benchmark end-to-end jobs, including data loading, checkpointing, orchestration and observability—not just a kernel microbenchmark.
- Budget engineering time for numerical validation when changing compiler, kernel or communication implementations.
Power, cooling and service requirements
Vera Rubin facility implications
The DGX Vera Rubin hardware guide describes liquid cooling through rack manifolds and cold plates. It specifies four power shelves, each rated at 110 kW, converting incoming AC to a 54-volt DC bus. These are equipment ratings and describe the rack’s power-delivery architecture; they are not a statement that every workload will draw 440 kW continuously.
A deployment must provide compatible liquid-cooling distribution, heat rejection, leak detection, electrical capacity, busway or cabling and service clearances. Facility engineers should use the final OEM configuration and local electrical standards rather than planning from a headline compute number.
Helios serviceability and open-rack planning
AMD highlights modular serviceability and integrated power, cooling and networking connections in an OCP Open Rack Wide form factor. The open mechanical standard may help organizations align Helios with existing rack programs, but it does not remove the need to verify coolant type, manifold connections, power shelves, firmware access and replacement procedures with the selected OEM.
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Questions to put in the site survey
- What is the rated and expected power envelope for the exact rack configuration?
- What supply and return coolant temperatures, flow rates and facility-side heat-rejection capacity are required?
- Can technicians replace a compute or switch tray without disturbing adjacent systems?
- What are the rack dimensions, floor-loading limits, overhead or underfloor distribution requirements and service clearances?
- Which network and storage uplinks are included, and which must be supplied by the customer?
Production status and procurement reality
NVIDIA says Vera Rubin is ramping into full production and shipping through manufacturing partners. AMD announced Helios in production in July 2026 and described customer deployments plus availability through infrastructure partners and OEMs including Bull, HPE, Lenovo, Supermicro, Sanmina and Wiwynn.
Those announcements establish each company’s public launch position. They do not prove equal shipment volume, installed base, lead time or availability in a particular country. A buyer should request a dated configuration, delivery schedule, warranty terms, spare-parts plan, software-support commitment and escalation path from the contracting supplier.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to decide which architecture fits a workload
1. Characterize the model before comparing racks
Record parameter count, precision, context length, batch size, optimizer state, activation checkpointing and KV-cache requirements. Determine whether the model and its working state fit within one rack’s aggregate HBM4 with practical headroom. A larger capacity figure can reduce model sharding, but only if the software can use that memory efficiently.
2. Define the success metric
Choose the metric that matters operationally: training tokens per second at a target sequence length, time to a quality threshold, inference tokens per second at a stated latency percentile, concurrent requests, energy per token or total cost per completed job. Record quality and precision constraints alongside speed.
3. Validate the software path
Run the actual framework, kernels, checkpoint format, quantization method and serving stack on each candidate. Include failure recovery, monitoring, job scheduling and image-build workflows. A theoretical port that requires rewriting custom kernels may cost more than a modest hardware difference.
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Measure all-reduce and other collectives at realistic tensor sizes, then run the complete distributed model. Capture utilization, synchronization time, inter-rack traffic and scaling efficiency as racks are added. Ask vendors to document whether quoted bandwidth is bidirectional, aggregate or effective.
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5. Engineer the facility
Obtain rack-level power, cooling, dimensions, weight, network and service requirements for the exact bill of materials. Confirm that liquid-cooling distribution and electrical systems can support the rack alongside existing loads and that technicians can safely service it.
6. Compare economics using the same assumptions
Use acquisition price, support, energy, cooling, floor space, staffing, software migration and utilization. Require the same model, precision, batch, latency target, power boundary and measurement period for both systems. Vendor claims about training with fewer GPUs or lower inference cost are conditional comparisons and should not be generalized beyond their stated assumptions.
How to read the headline performance numbers
AMD’s 2025 “Advancing AI” material previewed Helios with 2.9 EFLOPS FP4, 1.4 EFLOPS FP8, 31 TB HBM4, 1.4 PB/s memory bandwidth, 43 TB/s scale-out bandwidth and 260 TB/s scale-up bandwidth. The deck explicitly labeled those values as engineering projections subject to change. Current 2026 product pages and launch documents should take precedence, and the older figures should not be presented as measured results.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesNVIDIA and AMD both publish peak precision-specific figures. FP4, FP6 and FP8 throughput can be useful for understanding design targets, but models may use mixed precision, dequantization, memory-bound kernels or communication-heavy parallelism. Compare sustained end-to-end results at the precision and quality level you will actually deploy.
What the public material cannot establish
- There is no independently audited, matched-workload result in these product materials that makes one rack a universal performance winner.
- Aggregate HBM4 capacity does not reveal usable capacity after system reservations, partitioning or runtime overhead.
- Peak memory bandwidth does not predict application throughput without access-pattern and kernel data.
- CPU counts do not prove host-side performance, feeding efficiency or orchestration capacity.
- Launch and production statements do not establish your region’s orderability, lead time or installed-base support.
- Rack bandwidth totals with different counting conventions should not be converted into a simple ranking.
Bottom line for a systems buyer
Choose based on workload fit and deployment constraints, not on a single headline number. AMD Helios offers the larger published HBM4 pool and an UALink/UALoE, open-standard direction. NVIDIA Vera Rubin NVL72 offers a tightly integrated NVLink 6 rack with a documented tray, networking, liquid-cooling and power architecture, plus the CUDA platform. Both can be sensible choices for large-scale AI, but the winning system for your organization will be the one that meets model-memory needs, delivers measured throughput at the required latency, fits the facility and has a support path you can actually procure.
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