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NMOS and PMOS are the two channel polarities of MOSFETs: an enhancement-mode NMOS conducts when its gate is sufficiently above its source, while a PMOS conducts when its gate is sufficiently below its source. Their complementary behavior is the basis of common CMOS logic.

What NMOS and PMOS mean

Both are metal-oxide-semiconductor field-effect transistors (MOSFETs), in which the gate’s electric field controls whether a conducting channel connects the source and drain. NMOS means n-channel MOS; PMOS means p-channel MOS. The names describe the channel type and its majority carriers: electrons in an NMOS channel and holes in a PMOS channel.

In the introductory enhancement-mode structure, an NMOS has n-type source and drain regions in a p-type body. A PMOS has p-type source and drain regions in an n-type body. Integrated CMOS processes provide the complementary body regions using wells. The source and drain regions are similar in structure; their names describe their electrical roles in the operating circuit, not permanently different kinds of terminal.

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NMOS vs. PMOS at a glance

Feature NMOS PMOS
Channel polarity n-channel p-channel
Majority channel carrier Electrons Holes
Introductory source/drain doping n-type p-type
Introductory body doping p-type n-type
Enhancement-mode turn-on condition Gate-to-source voltage exceeds the NMOS threshold: VGS > VTN Source-to-gate voltage exceeds the magnitude of the PMOS threshold: VSG > |VTP|
Common digital schematic cue Usually shown without a gate bubble A gate bubble commonly indicates inverted control polarity

The gate-bubble convention is a schematic cue, not a substitute for checking the symbol and notation used in a particular circuit.

How the gate voltage controls each channel

NMOS: gate sufficiently above source

In the enhancement-mode model, raising the NMOS gate sufficiently above its source attracts electrons to the surface of the p-type body, forming an n-type channel between source and drain. The device can then conduct. The relevant comparison is gate-to-source voltage, not whether the gate is at some universally defined absolute “high” voltage.

PMOS: gate sufficiently below source

Lowering the PMOS gate relative to its source attracts holes to the surface of the n-type body, forming a p-type channel. It conducts when the source-to-gate voltage exceeds the magnitude of its threshold. Thus the familiar digital shorthand—NMOS turns on with a high input and PMOS with a low input—describes opposite control polarities in relation to their sources.

Threshold voltage depends on the device and fabrication process; there is no single threshold value that applies to every NMOS or PMOS. This explanation uses the common enhancement-mode model and does not cover depletion-mode devices.

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How NMOS and PMOS work together in CMOS

CMOS means complementary MOS: a circuit technology that uses both nMOS and pMOS devices. It is not another name for either transistor alone. In a simple CMOS inverter, a PMOS connects the output toward the positive supply rail when the input is low, while an NMOS pulls the output toward ground when the input is high. Their complementary switching produces the inverter’s opposite output state.

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This inverter is a basic illustration of complementary control, not a complete description of every CMOS circuit or every operating mode. Carrier type also should not be confused with conventional current direction: electrons and holes are the channel’s majority carriers, while conventional current is defined in the opposite direction to electron motion.

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What the distinction does—and does not—tell you

NMOS and PMOS identify channel polarity, majority carrier, and the direction of gate control in the standard enhancement-mode model. Those labels alone do not establish a universal ranking for drive strength, speed, or leakage. Such comparisons depend on fabrication technology and circuit design, and require device-specific information rather than a single general-purpose ratio.

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