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Microchip Technology’s data-center portfolio updates span the links that move data, the controllers that manage storage, and the components that power and monitor systems. The progression runs from a broad connectivity and storage announcement in April 2025 to PCIe Gen 6 switches, a Switchtec–Micron SSD demonstration in August 2026, and further Switchtec, Flashtec and Adaptec features in October 2026. These releases describe a portfolio strategy, not a single product that independently guarantees better AI or HPC performance.
What did Microchip update for AI data centers?
Microchip’s announcements cover several different jobs in a data-center system: PCIe interconnect, NVMe storage control, RAID, Ethernet connectivity, power conversion, timing, monitoring and platform management. The components are intended to fit into larger systems; their value depends on the host, storage devices, network, software and workload they are paired with.
| Product area | What it does | What Microchip announced |
|---|---|---|
| PCIe switching | Connects hosts and devices, and can support data movement between them. | Switchtec Gen 6 family with up to 160 lanes, announced in October 2025; a separate lower-lane-count PCIe 6.0 switch with up to 64 lanes and 32 ports, announced in October 2026. |
| Storage control | Manages NVMe SSD connectivity and controller functions. | Flashtec NVMe 5016 update with CNSA 2.0 support and dual-port capability, announced in October 2026. |
| RAID | Provides storage-array functions and management. | Adaptec SmartRAID 4300 enhancements including RAID 6/60, self-encrypting-drive key management and peer-to-peer rebuild. |
| Ethernet connectivity | Supports network signaling and switching at the Ethernet layer. | An 800G active electrical cable reference design using the META-DX2C retimer; META-DX2+ Ethernet PHYs with Lambda Splitting; and the LAN9646 six-port GbE switch. |
| Power and platform management | Supports power conversion, control, monitoring and auxiliary system management. | MCPF1412 power module, dsPIC33A digital signal controllers and OpenBMC-related MPUs, among other solutions. |
In its April 28, 2025 announcement, Microchip described Gen 3, Gen 4 and Gen 5 PCIe switches, with Gen 6 and Gen 7 technologies then in development. The release also covered NVMe storage and RAID controllers with hardware-based security, retimers, Ethernet PHYs, power management, system monitoring and precise timing. Those development-status descriptions reflect that 2025 announcement and should not be read as a current status for every product.
Connectivity and system components from the April 2025 portfolio
- 800G active electrical cable (AEC) reference design: Uses the META-DX2C 800G retimer with 112G SerDes. It includes software implementing CMIS 5.2 on a Microchip 32-bit microcontroller to support development of QSFP-DD and OSFP active electrical cables.
- META-DX2+ Ethernet PHY with Lambda Splitting: Microchip says the feature works with coherent optics to distribute traffic across wavelengths and can increase bandwidth efficiency by up to 50%. That is a company-stated capability, not an independently verified general result.
- LAN9646: A six-port Gigabit Ethernet switch with four integrated 10/100/1000BASE-T PHYs; SGMII, RGMII, MII and RMII interfaces; VLAN and QoS support; SPI and I²C management interfaces; Linux DSA compatibility; and a stated operating range of −40°C to +85°C.
- MCPF1412 power module: The release specifies up to 12 A output, an output range of 0.6 V to 1.8 V from a 16 V input, and a 5.8 mm × 4.9 mm × 1.6 mm package.
- dsPIC33A digital signal controllers: Presented for data-center and AI-server power-supply control, diagnostics, firmware attestation and device authentication.
- OpenBMC-related MPUs: Intended for auxiliary management in power shelves, enterprise storage, JBOD, cooling and chassis systems, with Redfish, out-of-band monitoring and secure-update functions described.
What is a PCIe Gen 6 switch used for?
A PCIe switch expands and manages connections between a host processor and PCIe devices, or between devices in a more complex system. In an AI or HPC server, it can form part of the path between processors and high-speed storage or other accelerators. The switch is one element in that path; the rest of the platform must also support the necessary PCIe generation, lanes, devices and software.
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Microchip’s October 13, 2025 Switchtec Gen 6 announcement describes PCIe 6.0 as providing 64 GT/s per lane, double the PCIe 5.0 rate. Microchip described its Switchtec Gen 6 family as built on a 3 nm process and supporting up to 160 lanes. The company also listed multicast, non-transparent bridging (NTB), error containment, diagnostics and support for ChipLink tools. It said the family includes hardware root of trust and secure boot with post-quantum-safe cryptography compliant with CNSA 2.0. These are vendor-reported specifications and feature claims, not independent comparative test results.
Two Switchtec Gen 6 announcements, with different scales
| Announcement | Scale and features described | What to keep in mind |
|---|---|---|
| October 13, 2025: Switchtec Gen 6 family | Up to 160 lanes; PCIe 6.0 at 64 GT/s per lane; security, multicast, NTB, error containment, diagnostics and ChipLink support. | Microchip said switches were available for sampling to qualified customers. It named the PM61160-KIT evaluation kit. |
| October 12, 2026: lower-lane-count PCIe 6.0 switch | Up to 64 lanes and 32 ports, with x2, x4, x8 and x16 bifurcation options; integrated DMA for peer-to-peer transfer; multicast, partitioning, hardware root of trust and secure boot. | These details are from Microchip’s announcement; confirm current part-level availability and compatibility for a specific system. |
Microchip attributes lower latency and higher throughput to the Switchtec Gen 6 switch and PCIe 6.0 features. Its October 2025 release also quotes data-center solutions executive Brian McCarson describing the family as enabling direct communication between compute resources and calling it the company’s most powerful and energy-efficient switch to date. Those statements express the vendor’s rationale and characterization; the cited announcements do not provide independent comparative benchmarks.
How does PCIe Gen 6 storage help AI and HPC?
AI training, inference and HPC jobs can involve moving large volumes of data among processors and storage. A faster interconnect may help remove a link bottleneck, but end-to-end performance also depends on SSD capability, host and switch configuration, workload behavior, software, and other parts of the data path. A PCIe 6.0 link specification alone does not establish how much a particular application will speed up.
On August 4, 2026, Microchip announced a demonstration with Micron that used Switchtec Gen 6 switches to connect host processors with multiple Micron 9650 PCIe Gen 6 NVMe SSDs. The companies described the architecture as supporting scalable, composable and disaggregated storage for AI, HPC and cloud data-center workloads. The release calls the Micron 9650 the first mass-produced PCIe Gen 6 SSD; that designation is the companies’ wording, not an independently established comparison here. A demonstration shows a system configuration, not a published comparative benchmark.
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- SATA 6Gb/s interface with sequential read speeds up to 555 MB/s and sequential write speeds up to 530 MB/s for consistent, high-throughput data access
- 3D TLC NAND flash with 1 Drive Write Per Day (DWPD) endurance rating and 7,008 TBW total write endurance over a standard 5-year period
- 96,000 random read IOPS and 35,000 random write IOPS with enterprise-grade power loss protection and error correcting code for data integrity in mission-critical environments
- Dual Dell/SK Hynix label (Dell DPN 03GDK0) — fully compatible with any system supporting a standard SATA interface, not limited to Dell systems; 2,000,000-hour MTBF reliability rating
The architectural point is that switching and storage work together: a switch provides connectivity among hosts and devices, while the SSD and its controller determine their own capabilities. System designers still need to validate lane allocation, topology, host support, software behavior, power and thermal requirements against the intended workload.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What changed in Flashtec and Adaptec storage products?
Microchip’s October 12, 2026 update also covered storage controllers and RAID management, which address different needs from the PCIe switch itself.
Flashtec NVMe 5016
Microchip described an enhanced PCIe Gen 5 NVMe Flashtec 5016 SSD controller with CNSA 2.0 support and dual-port capability. The company says dual ports can provide redundant paths and load balancing. A controller feature does not by itself ensure redundancy: the complete system must be designed and configured to use independent paths appropriately.
Adaptec SmartRAID 4300
The announced enhancements include self-encrypting-drive key management, RAID 6/60, dynamic NVMe configuration, persistent event logging, peer-to-peer rebuild and StorageCore API integration. Microchip also listed Linux, Debian, Ubuntu and Windows 11 support. Check compatibility for the exact controller, operating-system release, drive and management stack before deployment; the announcement does not establish support for every version or configuration.
How should a data-center team assess these updates?
These are product classes rather than consumer alternatives to rank against one another. Start with the system problem and validate the part against it.
- Define the function: Determine whether the need is PCIe switching, an NVMe controller, RAID, Ethernet physical-layer connectivity or switching, power conversion, or platform management.
- Check interface and scale: Match PCIe generation, lane and port count, bifurcation, Ethernet speed and interfaces to the host and attached devices.
- Map the workload and topology: Consider storage capacity and throughput, latency, host CPU involvement, peer-to-peer paths, and whether the design needs disaggregated or redundant storage.
- Review security and resilience requirements: Identify whether the design needs secure boot, root of trust, CNSA 2.0 support, drive-key management, RAID modes, error containment or diagnostics—and confirm how those features are implemented in the whole platform.
- Validate operational constraints: Confirm power, thermal, firmware, operating-system, driver and management-tool compatibility with the exact configuration.
- Confirm maturity and supply: Distinguish an announcement or demonstration from sampling and orderable production hardware. Microchip says pricing and availability vary by device and directs buyers to its sales representatives or authorized distributors; verify current status for the specific part and region.
What is established—and what still needs verification?
The cited releases provide vendor specifications, feature descriptions and a Switchtec–Micron system demonstration. They do not provide independent comparative benchmark figures that quantify performance gains across AI or HPC workloads. Treat claims such as lower latency, higher throughput, energy efficiency or bandwidth-efficiency improvement as Microchip’s claims unless validated for the intended configuration.
For an engineering decision, request the exact part number, current datasheet, sampling or production status, supported firmware and software, and region-specific supply information. Validate performance in the target system rather than inferring it from a lane rate or a demonstration architecture.
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