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Short answer: choose NVIDIA L4 for efficient, broadly supported inference; AMD Instinct MI300X when very large local HBM is the constraint; Google Cloud TPU v5p when you can standardize on Google’s cloud TPU software and pod topology; and MediaTek when you are prepared to co-design custom silicon and the surrounding rack for a specific workload. These are different procurement categories, so peak FLOPS alone cannot identify a winner.
These are four different ways to buy AI compute
The first decision is not between four interchangeable accelerator cards. NVIDIA L4 and AMD Instinct MI300X are merchant data-center accelerators that can be installed in servers. Google TPU v5p is a cloud infrastructure service organized into slices and pods. MediaTek’s offering is a custom-XPU and system-design engagement: the customer and MediaTek define the compute, memory, interconnect and rack architecture together.
| Option | What you acquire | Best initial fit | Primary constraint |
|---|---|---|---|
| MediaTek custom XPU | Workload-specific silicon and system co-design | Large, repeatable workloads where rack-level efficiency justifies a design program | Design engagement, lead time and non-standard procurement |
| NVIDIA L4 | Low-profile PCIe Gen4 x16 GPU | Inference, media processing and dense servers with modest power budgets | 24 GB device memory and PCIe-based scaling |
| AMD Instinct MI300X | CDNA3 OAM accelerator and eight-GPU platform | Large-model training or inference that benefits from very large local HBM | 750 W peak board power and the need to validate ROCm coverage |
| Google Cloud TPU v5p | Cloud TPU slices and pod-scale 3D-torus infrastructure | Organizations willing to run supported workloads in Google Cloud at pod scale | Cloud-only operating model and TPU-specific software and topology |
Use this distinction to avoid a common buying error: comparing a custom design, a PCIe card, an OAM platform and a cloud service as if they were prices for the same product.
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What the engagement includes
MediaTek describes a platform in which a customer can have the company architect the compute from the ground up or integrate the customer’s own AI accelerators, logic IP and microarchitectures into one system. The design can combine compute dies, HBM interfaces, other memory technologies, ultra-high-speed I/O and system-technology co-optimization.
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That makes MediaTek relevant when the workload and deployment plan are stable enough to justify custom engineering. The target is not a universal card that you order for a server; it is a design that can be tuned for a model family, a serving pattern, an interconnect, a power envelope and a complete rack.
Evidence of manufacturing activity
MediaTek reports more than 10 tape-outs on the N3 process and more than two on N2. It also says its first A14 test chip is taping out later in 2026. Those figures describe the company’s reported design activity, not a generally available data-center accelerator with published, comparable benchmark results.
Rack-level economics and NVLink Fusion
MediaTek identifies performance-per-total-cost and performance-per-watt as critical rack metrics. This shifts the analysis from a chip’s advertised throughput to how much useful work a complete system delivers for its capital, power, cooling and networking requirements.
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MediaTek also says it participates in NVIDIA’s NVLink Fusion ecosystem. The stated role is to connect custom XPUs with NVIDIA scale-up and rack architecture. That could matter if a custom accelerator must coexist with NVIDIA infrastructure, but the exact capabilities, availability and commercial terms are engagement-specific.
When custom silicon is justified
- Your workload is large, steady and valuable enough to amortize architecture, verification and tape-out costs.
- You can commit to model operators, precision modes, memory capacity and communication patterns for a meaningful product lifetime.
- Rack power, cooling or interconnect efficiency is more important than buying the fastest deployable card this quarter.
- Your organization can manage a multi-year hardware and software roadmap rather than a normal server refresh.
If those conditions are absent, a merchant accelerator or cloud TPU usually offers a faster path from software to production.
NVIDIA L4: the practical low-power inference card
Hardware profile
The L4 is a one-slot, low-profile PCIe Gen4 x16 card. NVIDIA lists certified server configurations containing one to eight GPUs, allowing operators to add inference capacity without adopting a specialized accelerator chassis.
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| Specification | NVIDIA L4 |
|---|---|
| FP32 | 30.3 teraFLOPS |
| TF32 Tensor Core | 120 TFLOPS |
| FP16/BF16 Tensor Core | 242 TFLOPS |
| FP8 Tensor Core with sparsity | 485 TFLOPS |
| Memory | 24 GB |
| Memory bandwidth | 300 GB/s |
| Board power | 72 W TDP |
| Host interface | PCIe Gen4 x16 |
Why it fits inference and media
A 72 W TDP and low-profile, single-slot format make the L4 suitable for dense servers, edge-adjacent data-center deployments and installations where each rack has a tight power or cooling budget. NVIDIA positions it for compute-intensive generative-AI inference and says it can deliver up to 2.5 times the performance of the previous GPU generation; that is a vendor comparison, not an apples-to-apples result against MI300X or TPU v5p.
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Where the L4 is a poor fit
Twenty-four gigabytes of memory limits the size of a model, batch or context window that can remain on one device. PCIe is also a different scaling model from the tightly coupled fabrics used by larger accelerator platforms. If your model routinely needs more than 24 GB per replica or demands high-bandwidth accelerator-to-accelerator traffic, plan for sharding, more cards or a different class of device.
AMD Instinct MI300X: maximum local HBM among these merchant options
Per-accelerator specifications
| Specification | AMD Instinct MI300X |
|---|---|
| Architecture | CDNA3 |
| HBM3 capacity | 192 GB |
| Peak HBM bandwidth | 5.3 TB/s |
| Peak FP8 performance | 2.61 PFLOPs |
| Host interface | PCIe 5.0 x16 |
| Peak board power | 750 W |
The 192 GB HBM3 pool is the MI300X’s defining buying argument in this comparison. A model that would need to be split across several 24 GB cards may fit on one MI300X, reducing cross-device communication and potentially simplifying serving. Capacity alone does not guarantee higher end-to-end throughput: kernels, precision, batching, sequence length and host networking still determine the result.
Eight-accelerator platform
AMD documents a platform of eight MI300X OAM accelerators with 1.5 TB of aggregate HBM3 and 20.9 PFLOPs of theoretical aggregate FP8 performance. That is a platform-level total, not the performance a single application will necessarily achieve. The platform also requires a power and cooling design capable of supporting up to 750 W per board, plus the infrastructure around eight high-power modules.
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ROCm is AMD’s software stack. Before purchase, test the exact framework versions, attention implementations, quantization path, collective-communication libraries and custom kernels used by your application. A model may run under ROCm while still lacking an optimized kernel for the operation that dominates your latency or training time.
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Google Cloud TPU v5p: a cloud pod with a specialized topology
Per-chip and pod specifications
| Specification | Google Cloud TPU v5p |
|---|---|
| BF16/FP8 performance | 459 TFLOPs per chip |
| HBM capacity | 95 GiB per chip |
| HBM bandwidth | 2,765 GB/s per chip |
| Bidirectional inter-chip bandwidth | 1,200 GB/s |
| Data-center network bandwidth | 50 Gbps |
| Pod size | 8,960 chips |
| Topology | 3D torus |
TPU v5p is not a PCIe card you install in an existing server. Google provisions slices and machine types in its cloud, with the 3D-torus topology providing tightly coupled communication between chips. This can be attractive for distributed training and large inference jobs when the application maps well to TPU software and the organization accepts Google Cloud as the operating environment.
Software and operational implications
You must plan around Google’s TPU software stack and the frameworks and compiler paths it supports. Porting a CUDA-oriented application is not a simple hardware swap: operators, precision behavior, input pipelines, collective operations and observability all need validation on TPU.
Cloud provisioning can eliminate hardware purchasing, facility power and physical installation, but it introduces cloud scheduling, quota, regional availability and egress considerations. Treat those as architecture requirements rather than details to solve after the model is ported.
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Generation trajectory
Google’s later Ironwood announcement describes 256-chip and 9,216-chip configurations and up to 7.37 TB/s of HBM bandwidth per chip. Those figures show TPU generations moving toward inference-oriented scale; they should not be substituted for the v5p specifications when sizing a v5p deployment.
Memory, bandwidth and throughput: how to read the numbers
The raw specifications differ in units and purpose. L4’s figures emphasize a low-power PCIe card. MI300X emphasizes very large HBM and high local bandwidth. TPU v5p combines substantial HBM bandwidth with a dedicated inter-chip fabric. MediaTek does not publish a fixed accelerator specification because the design is customized.
| Option | Memory per device | Memory bandwidth per device | Published accelerator throughput |
|---|---|---|---|
| NVIDIA L4 | 24 GB | 300 GB/s | 30.3 FP32 teraFLOPS; 120 TFLOPS TF32; 242 TFLOPS FP16/BF16; 485 FP8 TFLOPS with sparsity |
| AMD Instinct MI300X | 192 GB HBM3 | 5.3 TB/s peak | 2.61 PFLOPs FP8 peak |
| Google Cloud TPU v5p | 95 GiB HBM | 2,765 GB/s HBM | 459 BF16/FP8 TFLOPs |
| MediaTek custom XPU | Defined by the engagement | Defined by the engagement | Defined by the engagement |
These are vendor-published peak or theoretical figures with different precision formats, sparsity assumptions and system contexts. They are not an apples-to-apples application benchmark. Measure tokens per second, examples per second, time to train, tail latency, utilization and total cost for your own model.
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Choose by workload
High-volume inference with strict power limits
Start with L4 when the model fits within 24 GB or can be served efficiently with quantization and sharding. Its 72 W TDP, one-slot form factor and mature NVIDIA deployment stack favor dense, repeatable inference. Include video encode and decode in the evaluation if the service handles media, because that can remove a separate processing tier.
Large-model inference where memory is the bottleneck
Choose MI300X when keeping a large model in one 192 GB HBM3 address space is more valuable than minimizing board power. Compare the cost and latency of one MI300X against the number of smaller cards, memory copies and communication links required by an L4 design. Validate the complete ROCm software path before committing.
Distributed training at cloud scale
Evaluate TPU v5p when your training code can use the TPU compiler and supported frameworks and when pod or slice topology is an advantage. The 1,200 GB/s bidirectional inter-chip bandwidth and 3D torus are central to the design; they cannot be reproduced by treating a TPU slice as a collection of unrelated cards.
Stable, high-volume workloads with rack-level optimization goals
Consider a MediaTek custom XPU only after you can describe the workload, precision, memory footprint, communication pattern, service life and deployment volume well enough to guide a silicon program. The potential payoff is optimization across compute, memory, I/O, power and cooling, but the trade-off is design cost and a longer path to production.
Deployment, software and interconnect trade-offs
| Decision axis | MediaTek custom XPU | NVIDIA L4 | AMD MI300X | Google Cloud TPU v5p |
|---|---|---|---|---|
| Deployment | Custom design engagement | On-premises or colocated PCIe server | On-premises or colocated accelerator platform | Google Cloud service |
| Software | Co-designed stack; terms depend on project | CUDA, TensorRT and AI Enterprise | ROCm | Google Cloud TPU software and supported frameworks |
| Scale-up fabric | Custom rack interconnect; NVLink Fusion participation | PCIe in certified servers | AMD Infinity Fabric platform connectivity | 3D torus with 1,200 GB/s bidirectional ICI |
| Power profile | Optimized as part of the rack design | 72 W TDP | 750 W peak board power | Provisioned as cloud infrastructure |
| Procurement model | Engineering program and silicon roadmap | Buy accelerator-equipped servers | Buy accelerator-equipped servers | Provision capacity through Google Cloud |
The software row deserves as much weight as the hardware row. A theoretical advantage disappears if your framework, compiler, collective library or custom kernel is unsupported or requires a costly rewrite.
A practical selection process
- Define the service target. Record training time, throughput, first-token latency, tokens per second, batch size, sequence length, uptime and tail-latency limits for each production workload.
- Measure the memory requirement. Include weights, optimizer states, activations, KV cache, workspace and replication overhead. Compare the result with 24 GB on L4, 192 GB HBM3 on MI300X and 95 GiB HBM on TPU v5p.
- Map the software path. List framework versions, compiler, precision, quantization, attention kernels, collectives, data-loader behavior and monitoring. Run the real model rather than a small synthetic kernel.
- Choose the deployment boundary. Decide whether hardware must run in your facility, whether cloud operation is acceptable, and who owns driver, firmware, quota and capacity management.
- Size power and cooling. Model the complete server and rack. Eight MI300X accelerators, for example, imply eight boards each rated up to 750 W before adding CPUs, memory, networking and cooling overhead.
- Test scaling behavior. Measure single-device performance, multi-device communication, checkpointing, failure recovery and capacity under realistic concurrency. Do not extrapolate from one accelerator’s peak FLOPS.
- Calculate total cost of ownership. Include servers, networking, facility power, cooling, cloud charges, engineering, software support, utilization and the cost of unused capacity.
- Set a refresh and exit plan. Document how models will move to a newer GPU, TPU generation or custom revision, and how you will operate if a preferred cloud region or component is unavailable.
Common mistakes and how to avoid them
Comparing peak FLOPS as if they were benchmark results
FP32, TF32, FP16, BF16 and FP8 numbers measure different arithmetic paths. Sparsity can change the advertised result, and a model may be limited by memory traffic or communication. Use end-to-end workload measurements with the precision and sparsity pattern you will deploy.
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Ignoring model memory overhead
Weights are only one part of the footprint. KV cache can dominate long-context inference, while optimizer states and activations expand training requirements. Calculate the full footprint before selecting a device because a nominally adequate capacity may force expensive sharding.
Assuming software portability
CUDA, ROCm and TPU software are not interchangeable execution environments. Port a representative model, including custom operators and production preprocessing, before signing a capacity contract.
Underestimating facility constraints
A high-memory accelerator can reduce card count while increasing watts per board. Conversely, a low-power card may require more replicas. Compare useful throughput per rack kilowatt and per rack unit, not only throughput per device.
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Treating cloud and on-premises capacity as equivalent
TPU v5p capacity is obtained as cloud slices and pods with a defined topology. On-premises GPUs require procurement, installation, spare parts and lifecycle operations. Include provisioning time, quota risk and data movement in the same decision model.
What is established—and what still needs validation
The published specifications establish the form factor, memory, bandwidth, interfaces and vendor software direction described above. They do not establish a single winner for every model or a current transaction price across all four options. Availability, cloud rates, partner programs and framework support can change, so verify them for your region, software version and purchase date.
For MediaTek, the public information establishes a custom-XPU capability, reported tape-outs and NVLink Fusion participation, but not a standard SKU with fixed memory, bandwidth, price or benchmark results. Request those details under the design engagement before treating the option as a capacity source.
Bottom-line decision
Pick NVIDIA L4 when efficient, widely supported inference in ordinary PCIe servers is the priority. Pick AMD Instinct MI300X when 192 GB of HBM3 and 5.3 TB/s of local bandwidth can eliminate model sharding and your team is ready to validate ROCm. Pick Google Cloud TPU v5p when cloud operation, TPU software and 3D-torus scale match your training or inference system. Pick MediaTek custom XPU only when the workload volume and stability justify a silicon-and-rack co-design program. In every case, select on measured application throughput, memory fit, interconnect behavior, power and total cost—not on a peak-FLOPS leaderboard.
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