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Pat Gelsinger, Intel’s former chief executive, described high-bandwidth memory (HBM) as “a hideous memory” in an October 9, 2026 a16z Podcast discussion. His criticism was qualified: he also called HBM the best memory option currently available for demanding artificial-intelligence systems. Gelsinger’s objections concern engineering trade-offs—bit density, physical I/O (“shoreline”) bandwidth, power and thermals—not a claim that HBM is useless.

Separately, Nanya Technology’s forecasts point to continuing tightness across several conventional DRAM products. Nanya’s January 19, 2026 outlook identified DDR5, LPDDR5, DDR4, LPDDR4 and DDR3 as products that could face shortages, with limited new capacity expected in 2026 and the first half of 2027. A March 5 Taipei Times report attributed a broader forecast to Nanya in which the crunch could extend through 2028, with the most severe constraints expected through the first half of 2027.

What Gelsinger meant by “hideous memory”

In the surfaced transcript of the October 9, 2026 a16z Podcast episode, Gelsinger says, “And, you know, for that, as I’ve described, HBM is a hideous memory.” He immediately adds that it is the best available choice. The transcript is a third-party listing rather than an official transcript, so the exact punctuation should be checked against the original audio before being treated as a definitive quotation.

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His point is that HBM solves a pressing AI-system problem while imposing difficult manufacturing and system-design costs. Memory bandwidth can bottleneck memory-intensive AI workloads, and HBM places many memory connections close to the processor to increase throughput. The resulting package is valuable, but not simple or inherently efficient in every dimension.

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Bit density

Gelsinger cites poor bit density as one drawback. In practical terms, a system may obtain very high bandwidth without getting the same amount of storage capacity in a compact, inexpensive form. That can force designers to balance HBM with other memory tiers when models or datasets require substantial capacity.

Shoreline bandwidth and physical I/O

“Shoreline” refers to the physical edge and interconnect area available for wiring memory to a processor or package. HBM’s wide interface delivers bandwidth, but the number of connections, routing complexity and package constraints become significant engineering considerations. Gelsinger’s criticism is therefore about the physical cost of feeding the processor, not about bandwidth being unimportant.

Power and thermal behavior

HBM can improve data movement for AI accelerators, yet the memory stack, package and surrounding power-delivery design still generate heat. Gelsinger specifically identifies power and thermals as disadvantages. Those concerns matter because accelerators and memory operate together inside tightly constrained packages and servers; cooling and energy budgets affect the usable performance of the whole system.

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Why HBM remains important for AI hardware

Calling HBM “hideous” does not negate its utility. The same discussion frames memory bandwidth as a bottleneck in AI workloads and HBM as the best option currently available for addressing it. The technology’s value is that it supplies very wide data paths near the compute device, helping keep processors fed when workloads repeatedly move large volumes of data.

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The evidence available here does not include independent benchmark measurements comparing HBM with every alternative. It supports a trade-off analysis rather than a universal ranking: HBM is well suited to bandwidth-hungry AI systems, while its density, package, power and thermal compromises make innovation in other memory approaches worthwhile.

How the HBM trade-offs compare

Dimension What the evidence indicates about HBM Reader takeaway
Bandwidth Designed to address bandwidth bottlenecks in memory-intensive AI workloads. High bandwidth is the principal reason systems use it.
Physical I/O (“shoreline”) Gelsinger points to limits and complexity in the physical interface area and connections. More bandwidth can require demanding package and routing engineering.
Bit density He characterizes HBM’s bit density as poor. Bandwidth gains do not automatically provide maximum capacity per package or cost.
Power Gelsinger lists power as a concern. Memory performance must be weighed against system energy budgets.
Thermals He also identifies thermal issues. Cooling and package design remain part of the performance equation.

No comparative benchmark figures were provided with these remarks, so the table describes the stated engineering trade-offs rather than claiming measured performance differences.

Nanya’s shortage outlook covers more than HBM

Nanya’s January 19, 2026 investor presentation addresses several conventional DRAM categories, not just HBM. It says supply shortages may persist for DDR5, LPDDR5, DDR4, LPDDR4 and DDR3. The presentation also expects limited new supply capacity in 2026 and the first half of 2027. That is a dated company outlook, not a guaranteed market result.

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What “through 2028” refers to

A March 5, 2026 Taipei Times report attributed to Nanya a forecast that the DRAM supply crunch could continue through 2028, with the most severe constraints expected through the first half of 2027. The through-2028 wording should therefore be attributed to that reported company forecast. It is not an independently measured market-wide statistic, and it should not be presented as proof that every DRAM product will be scarce for the entire period.

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Why the product distinction matters

HBM is a specialized memory technology used alongside high-performance processors, whereas DDR5, DDR4, LPDDR5, LPDDR4 and DDR3 serve broader server, PC, mobile and embedded markets. Nanya’s January list establishes potential pressure across those conventional categories. It does not establish that HBM is the cause of every shortage, nor that shortages in one category automatically imply identical conditions in another.

Nanya’s planned capacity and what it does—and does not—solve

In an October 12, 2026 release, Nanya said its new fab is scheduled for equipment move-in in the first quarter of 2027. The company expects the facility to ramp to 30,000 wafer starts per month by the end of 2028 and 50,000 by the end of 2030.

These are forward-looking company plans. A planned ramp does not equal immediate market relief: equipment installation, process qualification, yield improvement and customer qualification all precede dependable high-volume output. The October release provides current fab-schedule context, but it does not itself restate the reported forecast that shortages will last until 2028.

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How to read the two stories together

  1. Separate technology from supply. Gelsinger is discussing HBM’s design compromises in AI hardware; Nanya is forecasting supply conditions across multiple DRAM products.
  2. Keep the time frames attached to their sources. Nanya’s January outlook covers limited capacity in 2026 and the first half of 2027, while the through-2028 statement comes from a March report quoting the company.
  3. Treat capacity plans as future supply, not present inventory. The new-fab targets are scheduled milestones and remain subject to execution.
  4. Avoid a single-cause explanation. The supplied statements do not show that HBM alone created the broader DRAM tightness.
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What this means for buyers and system designers

AI-system designers should view HBM as a performance-enabling compromise: its bandwidth can be essential, but package complexity, power, thermals and capacity density influence total system architecture. PC, server and mobile buyers should expect that pricing or availability for common DRAM generations may remain sensitive while suppliers add capacity, but neither Nanya’s outlook nor the reported forecast specifies a uniform shortage for every market or region.

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The clearest near-term signal is timing: Nanya expected constrained new capacity through the first half of 2027, while its reported longer-range forecast extended the crunch through 2028. The company’s fab schedule offers a path toward more supply later, with 30,000 monthly wafer starts targeted by the end of 2028 and 50,000 by the end of 2030.

Frequently Asked Questions

Did Pat Gelsinger say HBM has no value?

No. In the surfaced October 9, 2026 podcast transcript, he calls HBM “hideous” but also says it is the best memory option available. His remarks focus on bit density, shoreline bandwidth, power and thermal trade-offs.

Does Nanya’s forecast prove HBM is causing the DRAM shortage?

No. Nanya’s January outlook lists shortages across DDR5, LPDDR5, DDR4, LPDDR4 and DDR3. The available statements do not establish HBM as the cause of all DRAM supply constraints.

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When will Nanya’s new fab add capacity?

Nanya scheduled equipment move-in for the first quarter of 2027 and plans to reach 30,000 wafer starts per month by the end of 2028 and 50,000 by the end of 2030. These are company plans, not guaranteed immediate supply increases.

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