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IBM Research plans to release an early process design kit (PDK) for its 7-angstrom, or 0.7nm, Nanostack technology in the first quarter of 2027. The kit is meant for chip companies, electronic-design-automation (EDA) developers, equipment suppliers and research organizations that want to evaluate the architecture—not for ordering a finished commercial processor.
Nanostack is a research-stage, three-dimensional transistor architecture. IBM says it has demonstrated functional CMOS operation and projects major density, performance, energy and SRAM gains, but the first PDK will be intentionally incomplete and IBM has not announced mass-market manufacturing.
What IBM announced for Q1 2027
In its 13 October 2026 IBM Research release, IBM said it intends to make an early Nanostack PDK available during Q1 2027. A PDK contains the process models, design rules, cell libraries and related information needed to begin designing for a manufacturing technology.
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The first kit is an evaluation release. IBM expects it to contain exemplary standard-cell logic libraries and an exemplary SRAM design so users can test placement, routing, early block layouts and density, power and performance. IBM explicitly cautions that it will not include every model found in a mature commercial PDK.
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Jingyun Zhang, IBM Research senior technology enablement manager, described the goal as inviting organizations to participate in early evaluation and then “codifying the technology together.” He also said the PDK is intended to help designers migrate from conventional nanosheet technology to Nanostack.
How Nanostack changes transistor design
Nanostack is IBM’s nanosheet-based architecture with n-type and p-type devices vertically stacked and staggered. Conventional logic layouts are principally two-dimensional; Nanostack adds the z-axis at the transistor level.
That extra dimension can place more devices in a given footprint, but it changes the engineering problem. Designers must account for resistance and capacitance in the stacked paths, heat moving through upper and lower devices, and electrical interaction between devices that occupy different vertical positions. Zhang called the device structure “the biggest difference” and said logic layout is changing from 2D to 3D for the first time in foundry technology.
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The following numbers are IBM Research or IBM Newsroom figures published in 2026. They describe research results or projections, not benchmarks from a shipping product.
| Measure | IBM’s figure | Qualification |
|---|---|---|
| Transistors | Nearly 100 billion on a 150 mm² chip | IBM Research research result, 2026 |
| Density | Almost twice IBM’s 2nm node | IBM comparison, 2026; node names represent manufacturing generations, not literal wire widths |
| Performance | Up to 50% more | Projected comparison with IBM’s 2nm node |
| Energy efficiency | Up to 70% greater | Projected comparison with IBM’s 2nm node |
| SRAM scaling | 40% | IBM and VLSI-research figure, 2026 |
| Illustrative AI throughput | About 9,000 TOPS versus about 1,500 TOPS | IBM estimate for a 7-angstrom accelerator versus popular current accelerators; not a shipped-product benchmark |
“7 angstrom” is another way to write 0.7 nanometer. It should not be read as a claim that every transistor feature or metal line measures exactly 0.7nm. Modern node labels identify a process generation whose density, device structure and manufacturing rules are evaluated together.
Why IBM is targeting AI chips
AI accelerators move enormous volumes of data between compute units and memory. IBM connects Nanostack’s potential to three pressure points:
- More logic per area: higher density could fit more compute in the same package footprint.
- Lower energy per operation: IBM’s projected efficiency gain could reduce power for data-center workloads if it carries through to production designs.
- More on-chip SRAM: the reported 40% SRAM scaling could keep more weights, activations or intermediate data close to compute, reducing external-memory traffic.
IBM’s illustrative estimate says a 7-angstrom accelerator could reach roughly 9,000 TOPS compared with about 1,500 TOPS for popular AI accelerators. IBM also estimates that a frontier-model training run could fall from roughly three months to a couple of weeks. Both examples apply the research technology to current accelerator concepts; they are projections, not independent performance tests or announced products.
What has been demonstrated—and what has not
IBM says it experimentally validated key elements through ultra-thin dielectric wafer bonding, dual-channel engineering and functional CMOS inverter operation. Those demonstrations show that the device concept can be fabricated and switched.
They do not establish that a complete commercial processor can be manufactured at high yield, connected to production interconnects, cooled economically or supported by a full design ecosystem. IBM’s newsroom says an earliest production path could be as soon as five years, but that is a roadmap expectation rather than a committed manufacturing date. No customer chip or mass-production schedule has been announced.
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What designers can do with the early PDK
Organizations receiving the kit should treat it as an exploration environment rather than a tape-out-ready commercial platform. A practical evaluation flow would be:
- Import the process files and models into compatible design tools, checking which device, parasitic, thermal and reliability models are actually included.
- Build small standard-cell blocks with IBM’s exemplary libraries and verify placement and routing behavior in the vertically staggered geometry.
- Evaluate SRAM blocks using the exemplary memory design, measuring density and estimated power under the supplied assumptions.
- Run early floorplanning and extraction to study upper/lower-device interaction, resistance, capacitance and heat paths.
- Record model gaps and tool failures for IBM and EDA partners; the collaborative feedback is part of the purpose of an early PDK.
Results from this process will be useful for architecture decisions and tool adaptation, but they should not be presented as guaranteed production specifications while the kit remains incomplete.
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IBM identifies fabless chip companies, EDA vendors, semiconductor-equipment suppliers and research organizations as potential collaborators. The announcement does not publish a general public download process, pricing, eligibility rules or a referral program. Access should therefore be understood as an IBM-led early collaboration, with terms and availability to be confirmed by IBM.
The main engineering risks
- Thermal behavior: vertical devices can make heat removal and temperature uniformity harder than in a flat layout.
- Parasitics: new vertical connections and device interactions can erase some theoretical speed or energy gains if they are not modeled accurately.
- PDK maturity: limited models and exemplary cells cannot provide the sign-off confidence of a production PDK.
- EDA support: placement, routing, extraction, timing and verification tools must understand a transistor-level 3D structure.
- Manufacturing complexity: wafer bonding, alignment, yield and process control must be proven at scale.
These issues explain why the Q1 2027 release matters even without a commercial chip: it gives the ecosystem a way to expose design and manufacturing problems before a production commitment.
Bottom line on IBM’s 0.7nm Nanostack
IBM’s Nanostack is a credible research architecture with demonstrated CMOS building blocks and ambitious IBM projections: nearly 100 billion transistors on 150 mm², almost twice the density of IBM’s 2nm generation, up to 50% more performance or 70% better energy efficiency, and 40% SRAM scaling. The Q1 2027 PDK is the next step for collaborative evaluation, not evidence that 0.7nm processors are about to ship. Designers should judge the technology by the completeness of its models, tool support, thermal and parasitic results, manufacturing yield and eventual production schedule.
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